Breaking the 230Mbps barrier
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Axel Schumacher
Oct 14, 2016, 4:24:42 PM10/14/16
to FPGALink Users
Hi y'all,
I have a setup with an x86 machine sending data through USB, FX2LP with default FL firmware and parallel port to an FPGA with no back-pressure (h2fReady always on, writing to a GPIO).
With the commit 5520d3d (from 2014-04-02), I get data rates of 230Mbps (pretty close to Chris') when using the steps described here.
Is there a way I could increase the speed of the transfer? The Cypress document about raw bulk transfer over USB seems to claim they can reach 350Mbps (see figure 8).
Thanks!
Axel
Chris McClelland
Oct 14, 2016, 4:33:29 PM10/14/16
to fpgalin...@googlegroups.com
You need to use a more recent build of FPGALink. I switched bulk-endpoint pairs at some point[1], allowing for quad-buffering rather than mere double-buffering, and that increased the throughput from 25MiB/s to about 43MiB/s. I also switched the necessary connections between FX2 and FPGA. See section 4.1 of the user manual: http://www.swaton.ukfsn.org/temp/vhdl_paper.pdf
Chris
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Axel Schumacher
Oct 20, 2016, 1:37:51 PM10/20/16
to FPGALink Users
Awesome, thanks! I will give it a try.
On Friday, October 14, 2016 at 1:33:29 PM UTC-7, Chris McClelland wrote:
You need to use a more recent build of FPGALink. I switched bulk-endpoint pairs at some point[1], allowing for quad-buffering rather than mere double-buffering, and that increased the throughput from 25MiB/s to about 43MiB/s. I also switched the necessary connections between FX2 and FPGA. See section 4.1 of the user manual: http://www.swaton.ukfsn.org/temp/vhdl_paper.pdfChris
On Fri, Oct 14, 2016 at 7:57 PM, Axel Schumacher <axel.schum...@gmail.com> wrote:
Hi y'all,I have a setup with an x86 machine sending data through USB, FX2LP with default FL firmware and parallel port to an FPGA with no back-pressure (h2fReady always on, writing to a GPIO).With the commit 5520d3d (from 2014-04-02), I get data rates of 230Mbps (pretty close to Chris') when using the steps described here.Is there a way I could increase the speed of the transfer? The Cypress document about raw bulk transfer over USB seems to claim they can reach 350Mbps (see figure 8).Thanks!Axel
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ryan.ki...@planet.com
Feb 8, 2017, 1:32:24 PM2/8/17
to FPGALink Users
Hi Chris,
Hope you are well! Do you recall the conditions under which you measured a 43 MiB/s throughput? What OS was being used, and what did the USB bus topology look like?
Best,
Ryan
On Friday, October 14, 2016 at 1:33:29 PM UTC-7, Chris McClelland wrote:
You need to use a more recent build of FPGALink. I switched bulk-endpoint pairs at some point[1], allowing for quad-buffering rather than mere double-buffering, and that increased the throughput from 25MiB/s to about 43MiB/s. I also switched the necessary connections between FX2 and FPGA. See section 4.1 of the user manual: http://www.swaton.ukfsn.org/temp/vhdl_paper.pdfChris
On Fri, Oct 14, 2016 at 7:57 PM, Axel Schumacher <axel.schum...@gmail.com> wrote:
Hi y'all,I have a setup with an x86 machine sending data through USB, FX2LP with default FL firmware and parallel port to an FPGA with no back-pressure (h2fReady always on, writing to a GPIO).With the commit 5520d3d (from 2014-04-02), I get data rates of 230Mbps (pretty close to Chris') when using the steps described here.Is there a way I could increase the speed of the transfer? The Cypress document about raw bulk transfer over USB seems to claim they can reach 350Mbps (see figure 8).Thanks!Axel
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Chris McClelland
Feb 8, 2017, 1:52:31 PM2/8/17
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Hey Ryan,
I just used a regular desktop PC with Linux installed. I get that kind of throughput with the FX2 connected directly to the PC, and via a cheap hub. I have never tried measuring throughput on any Planet sats though so YMMV (probably best to test on a regular PC first). The only platform I've seen achieve significantly less than 40MiB/s is the Raspberry Pi, which has a shoddy USB host. Also bear in mind (sorry for the lawyer-talk) that USB bulk endpoints on which FPGALink is based make no throughput or latency guarantees: they get whatever bandwidth is left over after every other endpoint type has been serviced, so try disconnecting all the other devices from the root port, and try swapping cables too - the need for resends will hammer throughput.
Design-wise, the main thing to check is that your board (and its VHDL design) is definitely using the correct wiring for FIFOADR[1:0]: FIFOADR[0] needs to be low and FIFOADR[1] needs to be wired to the fx2FifoSel_out on the comm_fpga_fx2 module:
https://github.com/makestuff/comm-fpga/blob/20161106/fx2/vhdl/comm_fpga_fx2.vhdl#L29
Finally, make sure that the data stream is not being throttled by the FPGA itself. In other words, make sure that h2fValid_out and f2hReady_out are both high.
Chris
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ryan.ki...@planet.com
Feb 8, 2017, 2:14:37 PM2/8/17
to FPGALink Users
Hi Chris,
Thanks for the quick response. I have confirmed that we "did the right thing" with the FIFO_ADR signals. We've also checked that the FPGA isn't throttling by setting up a FIFO endpoint where f2hReady_out is always asserted.
Our next move seems clear: to test with a standalone PC and scrutinize what other endpoints are on the bus. Let the trace cutting begin. :)
Thanks again,
Ryan
Peter Stuge
Feb 11, 2017, 7:13:03 AM2/11/17
to fpgalin...@googlegroups.com
ryan.kingsbury via FPGALink Users wrote:
> Our next move seems clear: to test with a standalone PC and
> scrutinize what other endpoints are on the bus. Let the trace
> cutting begin. :)
All you really need is lsusb.
> Our next move seems clear: to test with a standalone PC and
> scrutinize what other endpoints are on the bus. Let the trace
> cutting begin. :)
Pretty much any live CD will be enough.
//Peter
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