Please read if you run FPGALink on a custom PCB
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Chris McClelland
Aug 27, 2012, 7:57:46 AM8/27/12
to fpgalin...@googlegroups.com
I noticed that when the libusb-0.1 bottleneck on the host side is
removed and replaced with the more efficient libusb-1.0 back-end, a new
bottleneck becomes significant - the fact that the CommFPGA protocol
uses USB endpoints 6 and 8.
Inside the FX2 chip, EP6OUT can be quad-buffered (basically a 2KiB
FIFO), but EP8IN is hard-coded so it can only be double-buffered at best
(a 1KiB FIFO). Since USB is kinda bursty, the amount of buffering is
significant: it means the difference between sustaining about 35MiB/s
and 43MiB/s.
I would like to switch the binary distribution to use EP2OUT and EP6IN
for both NeroJTAG & CommFPGA traffic, ensuring we have the maximum
possible buffering available in both directions.
This change will only affect you if you have designed your own PCB and
chosen to wire it in the FPGA-I/O-conserving configuration shown in the
2nd diagram in section 4.2 of the manual, i.e with FIFOADR[1] tied high,
with FIFOADR[0] driven by the FPGA. If this is you, please let me know.
I will then spend some time thinking about how to work around it. On the
other hand, if your board has *both* FIFOADR[0..1] lines wired to the
FPGA, this will *not* affect you.
The only such PCB that I *know* exists is one I designed myself, but if
there are no others, since I have only 20 prototypes of my board, I'll
probably just do some track-cutting and wire-modding, for shame, and fix
it on the next revision.
Obviously the idea solution is to make it configurable at runtime, like
the choice of JTAG lines is configurable, but I don't want to waste time
on it unless someone (apart from me!) actually *needs* it.
Chris
removed and replaced with the more efficient libusb-1.0 back-end, a new
bottleneck becomes significant - the fact that the CommFPGA protocol
uses USB endpoints 6 and 8.
Inside the FX2 chip, EP6OUT can be quad-buffered (basically a 2KiB
FIFO), but EP8IN is hard-coded so it can only be double-buffered at best
(a 1KiB FIFO). Since USB is kinda bursty, the amount of buffering is
significant: it means the difference between sustaining about 35MiB/s
and 43MiB/s.
I would like to switch the binary distribution to use EP2OUT and EP6IN
for both NeroJTAG & CommFPGA traffic, ensuring we have the maximum
possible buffering available in both directions.
This change will only affect you if you have designed your own PCB and
chosen to wire it in the FPGA-I/O-conserving configuration shown in the
2nd diagram in section 4.2 of the manual, i.e with FIFOADR[1] tied high,
with FIFOADR[0] driven by the FPGA. If this is you, please let me know.
I will then spend some time thinking about how to work around it. On the
other hand, if your board has *both* FIFOADR[0..1] lines wired to the
FPGA, this will *not* affect you.
The only such PCB that I *know* exists is one I designed myself, but if
there are no others, since I have only 20 prototypes of my board, I'll
probably just do some track-cutting and wire-modding, for shame, and fix
it on the next revision.
Obviously the idea solution is to make it configurable at runtime, like
the choice of JTAG lines is configurable, but I don't want to waste time
on it unless someone (apart from me!) actually *needs* it.
Chris
Henry Hallam
Aug 27, 2012, 10:37:16 PM8/27/12
to fpgalin...@googlegroups.com
I have a PCB with the wire saving configuration, but am going to respin it soon anyway so no big deal.
Henry
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Salmat
Aug 30, 2012, 1:09:21 AM8/30/12
to fpgalin...@googlegroups.com, fpgal...@m3.ath.cx
Hi,
I would be interested ! I have every pin connected with the FPGA, and throughput is important for me :)
Salmat
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