JTAG / cJTAG Electrical interface

[Ken Pettit]

Hey Gang,

Has anyone on the list given any thought to a two-wire electrical JTAG
interface? Or have the taped-out solutions to date all been the
standard 5-Wire JTAG implementation? I have the debugger in my core
basically working and was looking into a 2-wire interface given the
low-pin count on my ASICs.

Clearly SWD is out of the question with ARM IP protection. I see that
cJTAG (IEEE 1149.7) has been out for a number of years, but it appears
this was driven by TI in 2008-2010 timeframe, and there really hasn't
been any adoption of it. My guess is because of the added complexity of
the controller / state machines involved. Even TI doesn't seem to use
it much (their MSP430's use Spi-By-Wire vs. cJTAG). And OpenOCD has no
support for cJTAG other than a couple of TI parts, and even then, the
support is simply "Get this thing out of cJTAG mode and into JTAG".

So just curious if there had been any thoughts in this area. Perhaps if
there were an open core for cJTAG and open software support in OpenOCD,
maybe that would fuel better adoption?

Ken

[Tim Newsome]

Because of lack of OpenOCD support I haven't done much thinking around cJTAG. As you point out, cJTAG is significantly more complex than JTAG. I was also unable to find a debug device that we could use instead of the OpenOCD-supported ones that would allow for low-level cJTAG control. (If one exists, please point it out!)

My only real thought on cJTAG is that people who want it can use this IP to put a cJTAG controller in front of regular RISC-V JTAG: https://www.ip-extreme.com/IP/cJTAG.shtml

That doesn't really solve your problem, though.

I'm open to adding some kind of 2-wire DTM to the debug specification. High speed I2C is probably suitable. That does leave you with the problem of connecting it to gdb. The software implementation is probably not too hard. The hardware implementation also seems pretty doable. A board with USB, a bit-banging microcontroller (or FPGA), and a few GPIO pins should be enough. (RISC-V on an FPGA with some custom instructions would be a cool implementation.)

Would anybody be interested in pursuing this path?

Tim

Ken

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