RISC-V Debug Group

OpenOCD supports both system bus version 0 and version 1. Tim On Tue, Jun 11, 2019 at 1:00 AM Colin

I was drawing up an implementation of a debug spec compliant debug module for integration with an out

Hi Ray, I get your point but can understand that vendors are looking into SWD compatibility. It

These are some serious corner cases. :-) I agree with your interpretation, although the spec doesn

Maybe simpler as a truth table: allrunning allhalted Description 0 0 some but not all selected harts

Ok, thank you! But what about other cores? Does anyone of them implement it?

On Wed, 24 Oct 2018 at 05:23, Tim Newsome <t...@sifive.com> wrote: > > There are 2 ways to

Hi, I am trying to simulate the RISC-V rocket-chip with my environment based on Verilog. What I'm

Thanks Megan. It happens. ;-) Cheers, PA On 17/10/2018 00:23, Megan Wachs wrote: Shoot. You probably

Hello Tim and Tommy, Thanks for the answers, I'll try test it in coreplexip e31. Em segunda-feira

haltsum0 is required. I agree it would be better for it to be explicitly optional for single-hart

Hi all, Sorry for the late response... Please find attached a sample script file which demonstrates

Thanks Tim. Agreed. PA On 26/09/2018 04:08, Tim Newsome wrote: I think everybody is agreeing that WFI

I've created https://github.com/riscv/riscv-debug-spec/pull/369 to make this change. Tim On Tue,

Sorry for being too vague, Support for RISC-V debug via the Pulpino's Advanced Debug Interface as

Quoting a little more context, from the definition of the timing bit in mcontrol: 0: The action for

My kind of terms !! 😎 !! Justin James Bourne On Sun, Aug 26, 2018 at 8:24 AM <de...@groups.riscv.

Thank you. This makes sense. On Friday, August 24, 2018 at 6:28:18 PM UTC-4, Tim Newsome wrote: I

http://samsungteleportinfinite.com/ Justin James On Thu, Aug 16, 2018 at 8:19 AM <debug@groups.

On Wed, Aug 15, 2018 at 1:21 PM, <apr...@gmail.com> wrote: Hello, We need some clarification

If it's a write only register then there shouldn't be any requirement on the hardware to

https://github.com/riscv/riscv-debug-spec/pull/309 attempts to solve this problem by allowing

The spec doesn't say, but probably should. Ideally only the "before" triggers trip but

From the mcontrol timing field: A chain of triggers that don't all have the same timing value

The hit bit is only modified when a trigger hits (it is written to 1) or when the CSR is explicitly

Here's a real example: setting a memory access trigger on the address just below the stack, to

Thanks Palmer; Tim also replied, but not on list given he is traveling. The balance between

Depending on the configuration of sbcs ( sbreadonaddr , sbreadondata ), accesses to sbaddress0 and

Actually thanks for pointing this out, there is some confusion there because we are saying "

Hi, We do have support for RTT in theory. there was no RISC-V FPGA stream so far that supports "