Defect simulation (IEEE P2427) with ADMS

[camer...@gmail.com]

For anyone interested in using Xyce for defect coverage/yield analysis, I have a standing proposal for how to do the modeling using Verilog-AMS as part of P2427.

The methodology is to include a list of possible defects in the device models. It should be possible for ADMS to parse out that code and create multiple simulation models which you can swap between at runtime without having to restart.

If you want to see the proposal it's on iMeet..

https://ieee-sa.imeetcentral.com/p/aQAAAAAEUozv

Or I'll send you a copy if you are interested. P2427 is a slow moving beast, and we could be all done with support in Xyce before it hits the street...

P2427 - Standard for Analog Defect Modeling and Coverage

- that code make Xyce the first P2427 compliant simulator.

Kev.

[renaud...@gmail.com]

Hello,

I'd be interested to read about your proposal, however accessing it on iMeet is not really practical (need to register and not sure once registered I will get access to the particular project).

Can you send me a copy ?

Regards,

Renaud

[camer...@gmail.com]

[camer...@gmail.com]

That might seem like an overly simple proposal, but that was the intention - a defect is just the addition or removal of circuitry.

Ideally the defective versions of devices can be swapped for non-defective in a running simulation - just switch the device model code. Looping over a simulation switching models is a lot faster than creating different netlists for each defect.

[renaud...@gmail.com]

Interestingly, I have the impression that in VHDL-AMS, your proposal can already be implemented as the language supports the definition of multiple architectures for a block. I have never dug deeper into the practical aspects of making use of multiple architectures, and I am going to review the documentation with that in mind.

What about using a generate case statement in VerilogA to group the fault-free and faulty cases of a model in a single module ? I have seen examples where generate constructs are used to conditionally instantiate (sub-) modules (outside of the analog block). This has the advantage of already being present in the Verilog-AMS standard and supported in some commercial simulators  (in VerilogA). It would not require significant modifications in the parsers, only some conventions towards the simulator about the name of the variable to use to drive the case (and the defect activation)...  It would be nice that the case statement can be triggered by the simulator "dynamically" to activate a fault w/o interrupting a running transient (this capability corresponds to the fault-sensitivity analysis of Cadence).

Personally, from a readabiltiy standpoint, I would be more in favour of defining fault injection modules as some kind of wrapper that is substituted to original model in places where one wants to trigger fault injection. Then using  the case statement one could select to activate the fault-free or a faulty case. The implementation of most of these would just instanciate the original fault-free model, eventually adding a short or open defect instance or modifying a parameter. The code for the fault wrappers would be very easy to read (designers would appreciate), as all the complexity would be delegated to the original model module. 

Today, the fault templates as generated by Defectsim are totally unreadable for design engineers. In this respect, the proposal of storing fault information in a standardized language has a lot of merit.

Regards,

Renaud

[Kevin Cameron]

With the proposal as-is, you can view it as a bunch of wrapper definitions around the original device model.

I'm thinking some scripting at a higher level will let you switch models during simulation (maybe Python).

I'm not wedded to any particular way of doing this, but something that works with ADMS/Xyce and could be implemented easily for other simulators is what I'd like to get through the standards committee. Currently there's nothing on the table since they deleted my proposal. You are probably correct that the same thing could be represented in VHDL - the "-AMS" is unnecessary since all that's happening is that you are rewiring around the device model, there's no actual behavior in the defect description syntax.

I've built dynamic loaders for device models a couple of times, so you can do this stuff on-demand at runtime. In fact it's preferable to always do that, so you can eliminate all the constant parameters in the device models.

Regards,

Kev.

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[renaud...@gmail.com]

What about making a publication show-casing the ideas using VHDL-AMS syntax and VerilogA generate-case syntax ?

It will probably be welcomed in the scientific community and then this could be used to gain leverage in the P2427 circles.

Or maybe that the P2427 club is not the best place to do this -- maybe they are too much "test" minded, not enough "functional safety minded" ?

Renaud

[Kevin Cameron]

IEEE P2427 is the only game in town as far as standards go for analog defect analysis/coverage, getting a fresh PAR going, or trying to get stuff into the next rev takes too long.

I certainly won't be trying to do a mix of VHDL and other things, VHDL-AMS was very badly done and has no users I know of. Anything VHDL does, SystemVerilog now does too.

Mixed-signal tools is the weak spot for the EDA companies, and standards are how you take business away from them. Xyce is just another SPICE simulator for a lot of users, adding unique (and useful) functionality is where it can expand the user base of open-source EDA.

P2427 is only slightly involved with functional safety, but making Xyce the go-to electronics simulator for stuff like ISO26262 seems like a good direction for development.

Kev.

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[renaud...@gmail.com]

VHDL and VHDL-AMS are from "another era" in terms of programming paradigms. Clearly VHDL-AMS did not get much success, but I see this more as a marketing failure than a technical one. SystemVerilog has taken many of the concepts pre-existing in VHDL, and benefited from a well-oiled marketing machine from CDS.

But let's get back to the core topic: fault injection in  SPICE-like simulators using conservative connections and the continuous-time model of computation. This excludes SystemVerilog where the usage of conservative connections (using custom resolution functions lik EE-net) has remained marginal till now and where the model of computation for analog is discrete-time (as advertised in practically all CDS trainings -- check how they propose model capacitors...) or event--driven (never really seen yet).

What about making some demo's of the concepts you proposed using generate-case statements in VerilogA and architectures in VHDL-AMS (used for the sole reason that it supports multiple architectures in a way that comes closest to your initial proposal) ? These demo's could run in some commercial simulators and provide a kind of benchmark for an ADMS extension that would support the generate-case construct. The demo's could be based on the analog benchmarks provided by the P2427 workgroup.

[Kevin Cameron]

I have worked on commercial VHDL and Verilog simulators, VHDL-AMS was being created about the same time as Verilog-AMS. VHDL failed to address some technical issues and was always inferior at gate/transistor level, although I did try to get the fixes in a couple of times. Unlike Verilog-AMS there is no automated connection of analog & digital in VHDL (despite it being over two decades since that was invented).

SystemVerilog is now a bit more capable than VHDL, but has the same issues when it comes to behavioral modeling of transistors (other than the legacy built-ins from Verilog).

The mechanism you need for describing a defect in an HDL is a connection-break or component-removal along with insertion of new components. It's actually the same mechanism you need for back-annotation - which I had a proposal for in the '90s for Verilog-AMS.

That would normally only be a few weeks work in any committee, but P2427 has been going for 3 years and has produced little of value so far.

BTW, I did a event-driven model of a grounded capacitor using driver-access functions in Verilog-AMS sometime last century.

SPICE simulators aren't really "continuous time", it's the models that have that feature, and likewise it's the models that interact in ways that need solved to make things conservative. You can use analog simulators with discrete behavioral models that are neither of those things. I'd like to use Xyce with this technique -

http://www.v-ms.com/ICCAD-2014.pdf

With discrete models and parallel processing that'll give you much better results than Verilog for sign-off, particularly if you can get the back-annotation working (which is a reason for fixing stuff in P2427).

Kev.

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