Ah, that's the RXTX package which is required to handle serial
ports. Subtle documentation. You need to install from
http://rxtx.qbang.org/wiki/index.php/Download. I'm not sure what
it takes to install that on Windows. I hated using some
third-party add-on like this, but JAVA refuses to define an
interface and implementation for accessing serial ports.
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So, the documentation for this really blows, but I've not found a better solution. I think what you need is the rxtx-2.2pre2-bins.zip package, which contains files for Windows, Linux, MAC-OSX. For my x86_64 linux system, I installed these files into these locations:
/usr/lib/jvm/java-8-openjdk-amd64/jre/lib/ext/RXTXcomm.jar
/usr/lib/jvm/java-8-openjdk-amd64/jre/lib/amd64/librxtxSerial.so
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I've updated your image, http://sebhc.durgadas.com/mms89/images/cpm3-x2h8-ft245r-rtc.z67ide.xz. I made some long-intended changes so that the MODULES.COM command will show RTC and RAM drivers as well. I also added SPDSBC.COM to your image, and made some more reasonable default modes (I hope) for the Z37 drives. I forgot to change step rate, but am not sure what your drives support anyway.
H8 Console initialized!Hope it helps. Let me know if/when there's too much churn, and I can slow down updates to your image.
At some point, I am going to recreate this image from scratch,
and I'll partition it into 8x 8M partitions so there is less
wasted space. You can still choose how many of those partitions
are available in CP/M, and what drive letters they have. I'll also
setup CP/M 3 timestamps for the directories, unless you don't want
that. I need to re-test my scripts for creating an image from
scratch, and have now added the option to enable timestamps, so it
will be a good exercise either way - just whether or not you want
the image.
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This is great! Let me test this image and let’s make eventually such image the best it can be. The 8x 8M partitions along with three floppies + timestamp as the interrupt is available. I’m open to test any images you can make available to ensure proper operation with the H8.
Now that we have a working solution, I can start planning the new layout of the X2 controller along with the 256KB memory to support the H8.
Thanks for all your support!
Norberto
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This image is working great. I can read my floppy drives without any issue. Also modules is working fine. Thanks for adding the SPDSBC.COM file.
Great job Douglas.
For the new X/2 layout, any recommendation for improvements on such design? For sure, I will be using the 74HCT series if available.
Thanks,
Norberto
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You and I designed that 512K MMU last year, which I like. But if
you're making an X/2-H8 I'm guessing you'll be maintaining
software compatibility with that. I'll give it a little thought to
see if there's a way to extend the X/2-H8 MMU without breaking
compatibility. Being able to read and write different banks at the
same time can be a big benefit to CP/M 3 (and even RAM-disk
implementations). The ram-disk driver I did for the 512K MMU works
quite nicely.
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-------- Original Message --------
Subject: Re: [sebhc] CP/M3 CP/NET FT245 over USB performance
From: Douglas Miller <durga...@gmail.com>
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-------- Original Message --------
Subject: Re: [sebhc] CP/M3 CP/NET FT245 H8 Setup
From: Douglas Miller <durga...@gmail.com>
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Yes, I was thinking there must 512Kx8 RAM chips these days.
The /BANK line is the I/O port select, so I guess that's be your "normal" I/O port decode circuit. This one uses 8 ports. So, Address lines A3-A7, /IORQ, /WR combine to make /BANK. The MAP signal originates at the FlipFlop, being a latched version of D7 during output operations. Maybe you've got an earlier schematic? Attached is the one I have...
I think you were planning to make ROM-disable be orthogonal to bank select, but I'm not sure. I assumed that bit 5 of port 362Q selected/disabled ROM regardless of what RAM was selected. Otherwise, you'll have to route that between CPU and RAM boards.
The MAP signal is used to ensure that the board RESETs to the
"non banked" state, bypassing the MMU entirely. Only by writing
"1" to bit 7 (on every output) will the MMU stay enabled.
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