PyMTL Testbench Compatibility with VHDL

[Enze]

I'm interested in adopting PyMTL as a verification language as Python is substantially easier to use than Systemverilog.

My industry extensively uses VHDL, however, so PyMTL would need to be able to verify single-language and mixed-language blocks coded in VHDL.

Is there a good way to approach this with PyMTL? I've seen a VHDL2Verilog transpiler on Github, but it's unclear if it's mature enough to depend on for commercial projects, and whether it's really the optimal solution to add yet another compiler to the toolchain.

While I see PyMTL is focused on academic, architectural simulation, I will say that the defense industry is hungry for new tools like PyMTL to increase productivity but relies heavily on VHDL, so adding future support would have a huge, positive impact.

[Christopher Batten]

Hi Enze,

Thanks for reaching out! Unfortunately, I don't think there is an easy path to integrating VHDL into PyMTL, since we currently rely on Verilator for wrapping Verilog components. We will give it a bit more thought though.

Best,
Chris

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