PyMTL Testbench Compatibility with VHDL

36 views
Skip to first unread message

Enze

unread,
Feb 13, 2021, 3:19:50 PM2/13/21
to pymtl-users
I'm interested in adopting PyMTL as a verification language as Python is substantially easier to use than Systemverilog.

My industry extensively uses VHDL, however, so PyMTL would need to be able to verify single-language and mixed-language blocks coded in VHDL.

Is there a good way to approach this with PyMTL? I've seen a VHDL2Verilog transpiler on Github, but it's unclear if it's mature enough to depend on for commercial projects, and whether it's really the optimal solution to add yet another compiler to the toolchain.

While I see PyMTL is focused on academic, architectural simulation, I will say that the defense industry is hungry for new tools like PyMTL to increase productivity but relies heavily on VHDL, so adding future support would have a huge, positive impact.

Christopher Batten

unread,
Feb 13, 2021, 6:39:32 PM2/13/21
to Enze, pymtl-users
Hi Enze,

Thanks for reaching out! Unfortunately, I don't think there is an easy path to integrating VHDL into PyMTL, since we currently rely on Verilator for wrapping Verilog components. We will give it a bit more thought though.

Best,
Chris
> --
> You received this message because you are subscribed to the Google Groups "pymtl-users" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to pymtl-users...@googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/pymtl-users/a4e2dba2-5ec3-44f1-b8ec-969d0a8afca2n%40googlegroups.com.

Reply all
Reply to author
Forward
0 new messages