Icenowy Zheng
belum dibaca,21 Nov 2020, 19.39.1521/11/20Login untuk membalas kepada penulis
Login untuk meneruskan
Anda tidak memiliki izin untuk menghapus pesan dalam grup ini
Login untuk melaporkan pesan
Untuk melihat pesan asli, alamat email grup ini tidak boleh berstatus anonim atau Anda harus memiliki izin untuk melihat alamat email anggota.
kepadaMaxime Ripard, Chen-Yu Tsai, Jernej Skrabec, devic...@vger.kernel.org, linux-ar...@lists.infradead.org, inux-...@vger.kernel.org, linux...@googlegroups.com, Icenowy Zheng
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng <
ice...@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..3e7e99745b73 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,25 @@ usbphy: phy@1c19400 {
#phy-cells = <1>;
};
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
--
2.28.0