[PATCH 0/3] ARM: dts: sun8i: v3s: enable EHCI/OHCI

[Icenowy Zheng]

Formerly I forgot to add EHCI/OHCI0 device nodes to V3s DTs.

This patchset adds them, and switches PineCube to use only OHCI/EHCI,
not MUSB.

Icenowy Zheng (3):
ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
ARM: dts: sun8i: s3: switch PineCube to use OHCI/EHCI only

arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++-----
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
3 files changed, 39 insertions(+), 5 deletions(-)

--
2.28.0

[Icenowy Zheng]

The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.

Add the device nodes for the controllers.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..3e7e99745b73 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,25 @@ usbphy: phy@1c19400 {
#phy-cells = <1>;
};

+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
--
2.28.0

[Icenowy Zheng]

As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 2e4587d26ce5..0cd969194acb 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -77,6 +77,10 @@ red_led {
};
};

+&ehci0 {
+ status = "okay";
+};
+
&mmc0 {
broken-cd;
bus-width = <4>;
@@ -84,6 +88,10 @@ &mmc0 {
status = "okay";
};

+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
--
2.28.0

[Icenowy Zheng]

The PineCube board features a USB Type-A connector connected to the
SoC's USB pins.

As this is not designed for being used as a USB device, disable OTG
controller and route USB to OHCI/EHCI fixedly.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
---

arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
index 4aa0ee897a0a..c4177c54ef29 100644
--- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts
+++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
@@ -78,6 +78,12 @@ csi1_ep: endpoint {
};
};

+&ehci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";

+ status = "okay";
+};
+

&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
@@ -158,6 +164,12 @@ &mmc1 {
status = "okay";
};

+&ohci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";

+ status = "okay";
+};
+

&pio {
vcc-pd-supply = <&reg_dcdc3>;
vcc-pe-supply = <&reg_ldo3>;
@@ -224,11 +236,6 @@ &uart2 {
status = "okay";
};

-&usb_otg {
- dr_mode = "host";
- status = "okay";
-};
-
&usbphy {
usb0_vbus-supply = <&reg_vcc5v0>;
status = "okay";
--
2.28.0

[Chen-Yu Tsai]

On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng <ice...@aosc.io> wrote:
>
> The PineCube board features a USB Type-A connector connected to the
> SoC's USB pins.
>
> As this is not designed for being used as a USB device, disable OTG
> controller and route USB to OHCI/EHCI fixedly.

"Fixedly" does not mean what you likely intended here. "Permanently"
is probably closer.

However since the changes don't actually deal with the routing,
which IIRC is done in the PHY driver, I suggest just dropping
that part.


ChenYu

> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201122004011.1957325-2-icenowy%40aosc.io.

[Chen-Yu Tsai]

On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng <ice...@aosc.io> wrote:
>

> As the USB port on Lichee Pi Zero works in the OTG mode, enable the
> EHCI/OHCI controllers for it.

You should probably mention that the host controllers work better
than the OTG controller in host mode. Otherwise this change lacks
justification for enabling two extra hardware blocks.

ChenYu

> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com.

> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201122004011.1957325-1-icenowy%40aosc.io.

[Chen-Yu Tsai]

On Sun, Nov 22, 2020 at 8:39 AM Icenowy Zheng <ice...@aosc.io> wrote:
>
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng <ice...@aosc.io>

Acked-by: Chen-Yu Tsai <we...@csie.org>

[Icenowy Zheng]

于 2020年11月23日 GMT+08:00 上午11:37:43, Chen-Yu Tsai <we...@csie.org> 写到:

>On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng <ice...@aosc.io> wrote:
>>
>> As the USB port on Lichee Pi Zero works in the OTG mode, enable the
>> EHCI/OHCI controllers for it.
>
>You should probably mention that the host controllers work better
>than the OTG controller in host mode. Otherwise this change lacks
>justification for enabling two extra hardware blocks.

Our PHY driver do not sense whether ?HCI is enabled or not, so
for host to work it's necessary to be enabled, otherwise the phy
driver will just route USB to unenabled ?HCI and fail.

[Maxime Ripard]

Hi,

On Sun, Nov 22, 2020 at 08:40:11AM +0800, Icenowy Zheng wrote:
> The PineCube board features a USB Type-A connector connected to the
> SoC's USB pins.
>
> As this is not designed for being used as a USB device, disable OTG
> controller and route USB to OHCI/EHCI fixedly.

It's not designed to be used as one, but does it work? We've had a
number of boards where this happened in the past, and it was usable for
FEL, or any peripheral really.

If it did work, then this is a regression.

Also, you should explain why this is a good idea: if both can act as a
host, then why should we switch to the HCI controllers?

> Signed-off-by: Icenowy Zheng <ice...@aosc.io>
> ---
> arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
> index 4aa0ee897a0a..c4177c54ef29 100644
> --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts
> +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
> @@ -78,6 +78,12 @@ csi1_ep: endpoint {
> };
> };
>
> +&ehci0 {
> + phys = <&usbphy 0>;
> + phy-names = "usb";

This is weird to me to have the PHY set in the DTSI for musb, but not
for the USB controllers.

Maxime

[Chen-Yu Tsai]

On Mon, Nov 23, 2020 at 6:22 PM Icenowy Zheng <ice...@aosc.io> wrote:
>
>
>
> 于 2020年11月23日 GMT+08:00 上午11:37:43, Chen-Yu Tsai <we...@csie.org> 写到:
> >On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng <ice...@aosc.io> wrote:
> >>
> >> As the USB port on Lichee Pi Zero works in the OTG mode, enable the
> >> EHCI/OHCI controllers for it.
> >
> >You should probably mention that the host controllers work better
> >than the OTG controller in host mode. Otherwise this change lacks
> >justification for enabling two extra hardware blocks.
>
> Our PHY driver do not sense whether ?HCI is enabled or not, so
> for host to work it's necessary to be enabled, otherwise the phy
> driver will just route USB to unenabled ?HCI and fail.

So, this was never working in Linux to begin with? You should mention that.

Maybe a fixes tag is in order then.

[Icenowy Zheng]

于 2020年11月28日 GMT+08:00 上午11:09:17, Chen-Yu Tsai <we...@kernel.org> 写到:

Okay.

>
>Maybe a fixes tag is in order then.

Well I can't judge whether this is necessary.