Updates on VREG frying issues

[Ytai Ben-Tsvi]

Hey folks,

As some of you have noticed, we've had some recurring problems with the DC/DC regulator on the board getting fried during what appears to be normal usage.

With some help from my friends in Shenzhen, we now believe we understand the root cause of this issue. It has to do with the combination of large bulk capacitance with low ESR on the power input of the board and inductance of wires coming from your power supply. The net effect is that when connecting power to the IOIO, the input voltage may briefly jump to about twice its nominal value, exceeding the input voltage rating on the voltage regulator (which is 20V).

We are now working on a permanent fix, which is likely to require a board revision.

In the meantime, you can protect your board by:

• Try to use a lower voltage on the input, ideally 10V or less.
• If that is not an option, use wires that are as short as possible between your supply and the IOIO. Also, if you have an option to "soft start" the power supply (ramping the voltage over the course of a millisecond or so), do so.

Sorry about that. Will update when I have some news about a fix.

Ytai

[Bart den Hollander]

Maybe use a Elco between VIN and GND to create the soft start?

[Ytai Ben-Tsvi]

What's an Elco?

On Sep 24, 2013 7:40 AM, "Bart den Hollander" <hollan...@gmail.com> wrote:

Maybe use a Elco between VIN and GND to create the soft start?

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[Rod Dylan]

http://nl.wikipedia.org/wiki/Elektrolytische_condensator or more conveniently http://en.wikipedia.org/wiki/Electrolytic_capacitor .

[Ytai Ben-Tsvi]

I'm not sure how that helps:

If you connect it in parallel to the existing ceramic, the low ESR of the ceramic is going to dominate during inrush and the surge spike will still happen. If you connect it instead of the ceramic, its high ESR will create a lot of noise on the input rail, which may cause USB connection drops if Vin is close to 5V.

[kolbe]

Ytai,

Could you enter into more detail if possible?

Under 10V, OK... but any input on power cord lengths? Say with 9V how long can the cord be without risking damage.

Is there still a risk at lower voltages say 7.5V or 6V?

Does this problem exist for modern switching supplies?

The safest bet I guess is to just bypass the regulator and supply 5V to the board.

Maybe put this info as a sticky post.

[Ytai Ben-Tsvi]

If you're using 10V or less you can have the wires be as long as you want. If you're using more than 10V I'd be careful about wire lengths. I can give exact numbers, since they highly depend on the specific power supply that you're using: how fast it ramps up, how much current it can source during ramp-up, etc.

In practice, I've been using 12V, 2A wall adapters for a long time with a 1-meter long wire with no problem. LiPo batteries (3S-4S over long wires may be more of a problem.

[Paul McMahon]

Ytai,

have you come up with a solution to the problem, that might be rolled into a new version of IOIO?

I might be building a board which integrates IOIO with some other stuff, and wonder if you found some solutions to this issue, which don't restrict Vin or cable length.

thanks

[Ytai Ben-Tsvi]

This is still under investigation. The problem has now been narrowed down to be related to switching high loads when the input voltage is high. A solution has not yet been found.

If you're curious about the progress, you can track my post on the TI forum here:

http://e2e.ti.com/support/power_management/non-isolated_dcdc/f/196/t/390774

I'm pending on folks from SeeedStudio to provide some more measurements in order to be able to proceed.

For more options, visit https://groups.google.com/d/optout.

[Paul McMahon]

Ytai,

thanks for the link.  I'm glad to see this is still active.

I'm surprised you've narrowed it down to Load transients, since you had previously narrowed it down to spikes on Vin, and suspected long (inductive) power cables.

I have three suggestions, in case you have the ability to test different scenarios.

a) this one is a long shot, but it's easy, so could be worth a try.  The recommended design has a 0.1uF cap on Vin.  I don't know how this could cause the failure, unless there were a weird resonance building up inside the chip, which could be mitigated by the high-freq cap.

b) I've had numerous bad experiences with switching supplies running at high frequencies. They are very sensitive to layout and load transients.  I'm curious if the failure would occur at the low frequency setting.  To test this, connect FSW to PG or Vout.  Pretty tough with the QFN on IOIO, but maybe you have another vehicle to test it on.

c) Although it should not be required for this type of synchronous buck converter, The fact that the output drops might indicate the low-side output FET has blown closed.  I also seem to remember the measured resistance between SW and GND was very low on a failed device.  That being the case, it might be worth trying to protect that FET with a Zener, so that any voltage transients arising from abrupt changes in current through the inductor are clamped.

- Paul

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[Ytai Ben-Tsvi]

Thanks for your help. Inline.

<paul.mc...@gmail.com> wrote:

Ytai,

thanks for the link.  I'm glad to see this is still active.

I'm surprised you've narrowed it down to Load transients, since you had previously narrowed it down to spikes on Vin, and suspected long (inductive) power cables.

We've previously observed voltage surges exceeding (for a microsecond or so) the maximum rated input voltage. Since there were no other deviations from the specs, we have attributed the failures to those surges. Regardless of whether or not this was the problem, it is definitely a problem, thus we have revved the board to include a protection circuit for this case. After having verified that the surged are gone, we continued our tests to verify that the problem has gone and discovered that it hasn't. Moreover, we were able to demonstrate that we are presumably able to get the TPS to fail without exceeding its maximum ratings. We are trying to gather more data as requested by the TI engineers to find the cause and the cure.

I have three suggestions, in case you have the ability to test different scenarios.

a) this one is a long shot, but it's easy, so could be worth a try.  The recommended design has a 0.1uF cap on Vin.  I don't know how this could cause the failure, unless there were a weird resonance building up inside the chip, which could be mitigated by the high-freq cap.

Good point. I can see why this might explain the failure. I'll try that.

 

b) I've had numerous bad experiences with switching supplies running at high frequencies. They are very sensitive to layout and load transients.  I'm curious if the failure would occur at the low frequency setting.  To test this, connect FSW to PG or Vout.  Pretty tough with the QFN on IOIO, but maybe you have another vehicle to test it on.

I don't have a PCB where that's possible. I'm also not sure what I'll do with this information if I know. I'm been pretty careful about layout as I'm very well aware of how tricky it can be (learned the hard way...), but obviously fast switching circuits have a lot of advantages (much smaller / cheaper passives).

 

c) Although it should not be required for this type of synchronous buck converter, The fact that the output drops might indicate the low-side output FET has blown closed.  I also seem to remember the measured resistance between SW and GND was very low on a failed device.  That being the case, it might be worth trying to protect that FET with a Zener, so that any voltage transients arising from abrupt changes in current through the inductor are clamped.

If you're referring to the graph posted on the TI forum, to me it looks like the output capacitor being drained by the load as opposed to a hard pull-down by a blown low-side FET. Zeners are not usually effective for such protection, but rather two Schottkys (GND to SW, SW to Vin), but since the datasheet doesn't call for them, I'm assuming the body diodes of the FET and/or the synchronous operation of the high-side/low-side FET doesn't require them.

[Paul McMahon]

Comments inline...

On Sunday, February 1, 2015 at 1:15:12 AM UTC-5, Ytai wrote:

Thanks for your help. Inline.

<paul.mc...@gmail.com> wrote:

Ytai,

thanks for the link.  I'm glad to see this is still active.

I'm surprised you've narrowed it down to Load transients, since you had previously narrowed it down to spikes on Vin, and suspected long (inductive) power cables.

We've previously observed voltage surges exceeding (for a microsecond or so) the maximum rated input voltage. Since there were no other deviations from the specs, we have attributed the failures to those surges. Regardless of whether or not this was the problem, it is definitely a problem, thus we have revved the board to include a protection circuit for this case. After having verified that the surged are gone, we continued our tests to verify that the problem has gone and discovered that it hasn't. Moreover, we were able to demonstrate that we are presumably able to get the TPS to fail without exceeding its maximum ratings. We are trying to gather more data as requested by the TI engineers to find the cause and the cure.

I have three suggestions, in case you have the ability to test different scenarios.

a) this one is a long shot, but it's easy, so could be worth a try.  The recommended design has a 0.1uF cap on Vin.  I don't know how this could cause the failure, unless there were a weird resonance building up inside the chip, which could be mitigated by the high-freq cap.

Good point. I can see why this might explain the failure. I'll try that.

 

b) I've had numerous bad experiences with switching supplies running at high frequencies. They are very sensitive to layout and load transients.  I'm curious if the failure would occur at the low frequency setting.  To test this, connect FSW to PG or Vout.  Pretty tough with the QFN on IOIO, but maybe you have another vehicle to test it on.

I don't have a PCB where that's possible. I'm also not sure what I'll do with this information if I know. I'm been pretty careful about layout as I'm very well aware of how tricky it can be (learned the hard way...), but obviously fast switching circuits have a lot of advantages (much smaller / cheaper passives).

 

Well, the 'what you would do', would be to choose the lower frequency setting on a future version of the board.  Too bad there's no easy way to test it.

 

c) Although it should not be required for this type of synchronous buck converter, The fact that the output drops might indicate the low-side output FET has blown closed.  I also seem to remember the measured resistance between SW and GND was very low on a failed device.  That being the case, it might be worth trying to protect that FET with a Zener, so that any voltage transients arising from abrupt changes in current through the inductor are clamped.

If you're referring to the graph posted on the TI forum, to me it looks like the output capacitor being drained by the load as opposed to a hard pull-down by a blown low-side FET. Zeners are not usually effective for such protection, but rather two Schottkys (GND to SW, SW to Vin), but since the datasheet doesn't call for them, I'm assuming the body diodes of the FET and/or the synchronous operation of the high-side/low-side FET doesn't require them.

I should have said Schottkys, not a Zener.  Did TI ever do a failure analysis of a failed part for you?  We really need to know if it's the input side or the output side that suffered the electrical stress.  Did you ever measure the resistance between SW and GND on a failed part?

As for the body diodes, they may have become the current path in the case where the low-side FET didn't turn on as quickly as it should.  The idea is that the external Schottky could give an alternate path for the current, just until that lower FET turns on.

 

[Ytai Ben-Tsvi]

Lower frequency means bigger and more expensive passives. The high frequency should work if done properly. I would like to understand what I've done wrong. Your catch of the missing capacitor is a promising candidate.

I haven't tried to analyze failed parts - it is a good idea and I'll do it.

I think that the voltage surge on the SW node is a low-likelihood failure mode, as it would indicate a serious design flaw in the switcher. Noise on the analog supply rails which might throw regulation out of stability or failure to detect an over-current condition is a more plausible explanation IMO.

Appreciate your feedback. You might have solved the issue. I'll spin another prototype rev soon and we'll find out.

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