Hi Taka and Group,
This weekend I tried the same experiments Taka performed and saw similar results. I also checked to see if the bias current had any effect. For example, we set the bias to 100mA per LDMOS transistor. Does setting this higher to 110mA or 120mA help? I saw little change when varying the bias current. I also checked temperature and saw that once warm, the timing does improve. For example, after key down for 10 seconds, the next key down does not show as significant of a problem. I substituted 4.7nF for B109 and saw significant improvement. If testing with 4.7nF shows no other problems over the next few weeks, then we will switch to that for the next build. CW operators may want to consider changing out B109 for 10nF or 4.7nF on existing boards.
Worst case cold start with existing 100nF B109. Note the time scale is 10ms and it takes 60-70ms for the bias to reach full level. You can see the effect on the CW tone with the extra shaping. TX buffer latency is set to 6ms for relay settling.
Below is what hot start with existing 100nF B109 looks like. Now the horizontal time scale is 2ms and the bias has almost reached max at 6ms. There is still a little shaping due to the bias rise.
Below is what cold start looks like with 47nF B109. Note that the bias is stable within 4ms. I'm not sure what the glitch is at about 5V but it is seen every time, even when 100nF was used.
73,
Steve
kf7o