Hermes-Lite Beta3 Schematic

[Steve Haynal]

Hi Group,

A pdf version of the beta3 schematic is now available on github or via the main web site: www.hermeslite.com. It should contain most of what is planned for beta3. One thing missing is some pin reassignments to the FPGA from the AD9866 to avoid high capacitance pins and allow for true half duplex again. I have this worked out but haven't updated this schematic with the new pin assignments. The BOM and PCB are not updated. I'd appreciate any review of and feedback on this schematic. Below are my notes of all changes. 

The next step is to start on the PCB changes. Note that all the changes in the schematic should only result in only minor changes to the pcb layout.

73,

Steve

KF7O

* Power

** AP2204 for Vop included by default

** AP2204 uses main input power

** Optional sync clock removed from U8 PA power supply, used as AP2204 enable

** Capacitor and TVS added to power input. TVS can be SMBJ20C or similar

** 8V for PA

** 10.15V for OpAmp/Bias

* PA

** Removed bias regulator U14, sharing 10.15V Vop regulator

** U15 switched to MCP4662 rheosat, exact part MCP4662-502E/UN

** Bias resistor divider per Claudio's post

** FPGA pin 39 was bias on/off, now separate IO for external TR switch separate from onboard TR swithc. This is is so full duplex can be run externally, otherwise TR always switches onboard relay too.

** Added INA199 and current sense resistor

* RFFE

** Added 0.1uF near preamp opamp power

** Moved C55 to otherside of T2 to improve RX. C55 left in place but DNI. New C87 is 8.2pF per Claudio's experiments.

* Input/Output

** Added connection for Vipa for voltage indicating PA current

** Converted op amp channels 3 and 4 for temp and PA current to follower with LPF

** Added optional extra ESD protection on front-panel IO. Multiple common SOT-23 devices possible for easy soldering.

** Lowered resistance and RC constant on all IO to allow for faster (CW) signal switching.

[James Ahlstrom]

Hello Steve,

On Monday, May 22, 2017 at 1:14:17 AM UTC-4, Steve Haynal wrote:

* PA

** Removed bias regulator U14, sharing 10.15V Vop regulator

** U15 switched to MCP4662 rheosat, exact part MCP4662-502E/UN

** Bias resistor divider per Claudio's post

On the Power Amp page, the text under U15 says " R101,R95,R47,R56 set for AFT05MS003", but it should say R66 instead of R56.

On U15, the address pins result in an I2C address of 0b0010_1100 or 0x2C, not 0x28 according to the data sheet table 6-2 on page 50.

Nice work Steve!

Jim

N2ADR

[in3otd]

Hello,
regarding the LED, there was some discussion about changing the resistor values and maybe the voltage, for the Ethernet LEDs, do you plan to do some changes there?

Looking at the CN6 connector (unchanged from the beta 2 revision), it says "4 LEDs or optional internal IO" but is not clear to me how the IO function will work, by placing a 0-ohm jumper instead of a LED? Will not be easier to connect CN6 directly to the FPGA IO/s?

73 de Claudio, IN3OTD / DK1CG

[Steve Haynal]

Thanks. Changes made.

73,

Steve

KF7O

[Steve Haynal]

Hi Claudio,

Thanks for reminding me about the LEDs. As discussed, I changed the Ethernet LEDs to use the 3.3V supply. I changed the 4 FPGA LEDs to use 1K as that is what Dani tested. He said it might be possible to go to 2.2K. I will if someone tests that.

The option to use of the 4 LED IO as alternate IO was because there was room in that part of the PCB and some people (I believe Taka) want extra IO to an I2S interface. Someone who wants to tweak the firmware can remove some or all of the LEDs and have extra IO. I moved the connector to be direct to the FPGA as you suggest.

73,

Steve

KF7O

[Steve Haynal]

Hi All,

Regarding the bias, I think there was some discussion that impedance for the DC bias could be too high. Claudio and Jim, are you comfortable with the impedance of the new circuit? Claudio, have you tested it?

Designs such as the KX3 have an additional 100Ohm to the gate with a 0.1 uF capacitor on the non gate side of the resistor. Do you think we should do something similar?

73,

Steve

KF7O

[Dani EA4GPZ]

El 23/05/17 a las 06:36, Steve Haynal escribió:

> Hi Claudio,
>
> Thanks for reminding me about the LEDs. As discussed, I changed the
> Ethernet LEDs to use the 3.3V supply. I changed the 4 FPGA LEDs to use
> 1K as that is what Dani tested. He said it might be possible to go to
> 2.2K. I will if someone tests that.

Hi all,

I might try 2.2K over the week and come back with the results.

Regards,

Dani.

[James Ahlstrom]

Hello Steve,

On Tuesday, May 23, 2017 at 12:39:57 AM UTC-4, Steve Haynal wrote:

Designs such as the KX3 have an additional 100Ohm to the gate with a 0.1 uF capacitor on the non gate side of the resistor. Do you think we should do something similar?

The 5000 ohm resistance of U15 is the minimum value, so I don't see how to lower the DC impedance without making things more complicated.  I do think it is useful to move B109 and B110 to the other side of R47 and R66, and then insert a resistor of a few hundred ohms to the gate.  This is more like what I have seen in other circuits, but I have no measurements.

Jim

N2ADR 

[Takashi K]

Hi Steve,

 

> The option to use of the 4 LED IO as alternate IO was because there was room in that part of the PCB

> and some people (I believe Taka) want extra IO to an I2S interface.

Just information.

I will use CN4 and CN5-7pin for I2S, DB1 for audio codec I2C (share with clock gen.). So CN6 is spare(LEDs) now.

73, Taka  ji1udd

[Steve Haynal]

Hi Group,

I've updated the beta3 schematic with the new FPGA connections as wells as the issues that came in the last few days.The date on the latest schematic is 2017-05-23. For comparison, the beta2 schematic as pdf is still on github as hermeslite.beta2.pdf.

Main site: www.hermeslite.com

Github: https://github.com/softerhardware/Hermes-Lite2/tree/master/hardware/hl

Please let me know if you see any problems.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Since the 5V bias regulator is removed in beta3 there is some extra room in that area. I added 100 Ohm resistors to the LDMOS gates with 0.1 uF on the nongate side. These can always be stuffed as 0 Ohm and no capacitor. I also added optional footprints for parallel resistors with the mcp4662 U15 so the overall resistance can be lowered if needed.

Main site: www.hermeslite.com

Github: https://github.com/softerhardware/Hermes-Lite2/tree/master/hardware/hl

73,

Steve

KF7O

[in3otd]

Hello,
the bias network DC resistance is important for PAs with bipolar devices, whose base current change with the drive level. The low-frequency impedance of the bias network may be important to reduce the IMD at higher power levels - AFAIU, the theory is to avoid that the intermodulation products at low frequency mix up with the fundamental to create additional intermodulation. Here the gates "see" also the input transformer and driver impedance which helps keeping the LF impedance down: a differential signal on the gates sees the output impedance of the driver, a common mode signal (the even-order harmonics) currently sees a high impedance. To keep the impedance low for common-mode signal the transformer should have a center tap. I'll try to so some measurements in the next days to see if all this is really important.

Besides, for the INA199 the datasheet says that the lowest output voltage is typically 5 mV, 50 mV worst case, with a 10 kohm to GND; I was wondering whether this pull-down resistor is needed to guarantee that the output will go that low or was specified just to assume some loading at the output.

73 de Claudio, IN3OTD / DK1CG

[in3otd]

uhm, I changed the Magjack LEDs resistors supply to 3.3 V and then the ethernet interface was not working anymore, the Link LED was on but no address was assigned. It seems that something does not work well with the new supply, maybe the LED pins are not read correctly during reset and the wrong PHYAD is assigned; disconnecting R30 everything works fine again. Maybe this is due to power supply sequence/relative timing between the 3.3 V and 2.5V ?
Steve, does the FPGA reset the PHY at power up or the reset comes just from the RC network? I did not try to reset the PHY manually, I wasn't sure if the FPGA was actively driving the reset signal and wanted to avoid shorting an output.

At least the Activity LED is quite brighter now, hi.

73 de Claudio, IN3OTD / DK1CG

[Takashi K]

Hi,

Regarding PHYAD setting, using pull-up seems to improve robustness.

73, Taka  ji1udd

[irbsu...@yahoo.co.uk]

Hi Steve,
One suggestion, I would find it helpful if the dcdc converters had either zero ohm links or ferrites in series with their outputs. This is so that they can be tested for correct output levels in isolation without danger of damaging the FPGA, CODEC etc (I usually build the power supplies and check them first).
Several of the devices can be isolated by not fitting series ferrites but not everything.
Just a thought,
Andrew
G4XZL

[Steve Haynal]

Hi Claudio,

It is just the RC network for the PHY reset. Currently, the pin on the FPGA is configured as an input. It is there so that the phy reset can be driven if needed.

I need to take a closer look at some other designs that use the KSZ9031 and try the 3.3V myself. I'm not sure I want to change the PHYAD so that we can use the pull-up configuration. I may just leave the current resistors for 2.5V pullup but also add alternate resistors footprints for 3.3V pullup.

73,

Steve

KF7O

[Steve Haynal]

Hi Taka,

This would also change the phy address. I have to check the firmware to see if this causes problems.

73,

Steve

KF7O

[Takashi K]

Hi Steve,

Maybe you know, If both PHYAD1 and PHYAD0 are pulled up, I think HLv2 firmware should be changed as following;

file : mdio.v, line 50 and 51

wire [63:0] wr_bits = {32'hFFFFFFFF, 9'b010100111, addr, 2'b10, wr_data};
wire [63:0] rd_bits = {32'hFFFFFFFF, 9'b011000111, addr, 2'bxx, 16'hFFFF};

I have not checked if  PCB layout modification is easy and I can accept the current design ( a bit dim LED ) .

So I don't recommend pull-up setting strongly.

73, Taka  ji1udd

[Steve Haynal]

Hi Andrew,

I've added an issue and will consider this as I work on the beta3 PCB changes. I usually build the power supplies first so that they can be tested in isolation.

73,

Steve

KF7O

[Steve Haynal]

Hi Taka and Claudio,

Thanks. I think you are right that is the only place the firmware needs to be changed. Why do you think a pull up configuration will be more robust?

I think I am going to punt on this issue for now unless someone else does more experiments. There appears to be space in that area of the PCB so I will just add footprints so that the PHY LEDs can be configured with 3.3V or 2.5V supplies, and maybe pullup or pulldown address configuration. This is actually easier for me to do then hack my beta2 board now. We can sort out the best build on real beta3 boards. Ideally, I'd like to not have the current hungry LEDs off of the limited 2.5V supply.

73,

Steve

KF7O

[Takashi K]

Hi Steve,

> Why do you think a pull up configuration will be more robust?

Regarding pull down configuration, R30 and R31, MagJack LEDs work as pull-up in spite of intention of PHYAD pull down setting. Therefore it is necessary to consider the voltage balance between pullup side and pulldown side.

I think Veth 2.5V operation is no problem because LED Vf is around 2V. But Veth 3.3V operation, especially when LED is 3.3V and KSZ9031 I/O power is 2.5V, if LED Vf is low side, KSZ9031 might recognize as "H" level.

FYI, Realtek PHY, RTL8211's LED port has strap function as same as KSZ9031. But the specification is improved to avoid this issue. Please refer to the attached png file.

73, Taka  ji1udd

[in3otd]

Hello,
did some measurements on the PA to check the effect of the gate bias resistor. The PA was driven by external signal generators thru a transformer since this allows more flexibility on the input levels and frequencies for two-tone tests.
While doing the tests I saw (again) some anomaly in the IM3 of the PA, than can be seen also in the previous measurements here; the intermodulation has a small hump between 10 dBm and 20 dBm output.

Below is the measured IM3 for different values of the gate bias resistor and also with a choke (3 turns on a Bourns FB73-422 ferrite) instead of a resistor; every case measured with the input transformer center tap connected to ground ('CT' cases) or not.

most evident thing is the strange IM3 behavior around 15 dBm output - more on this later - so look only at the portion above 20 dBm out. It seems that a high-value gate bias resistor helps to reduce the IM3 - I don't know why - and 100 ohm is the worst case (besides causing a lower gain due to the increased load on the input).
Note also that with the input transformer center tap to ground the IM3 is generally worse but we don't use a transformer when driving the PA with the opamp drive (I mixed up things in my previous email). On the other hand, the second harmonic is reduce when grounding the center tap (graph available on request, hi)

Regarding the IM3 peaks and dips, at first I thought they could be due to some parasitic oscillation but was a bit puzzled since I never saw any oscillation from these devices before, the spectrum analyzer was not showing anything besides the test signals and their products and touching the PCB around the PA did not change anything. Moreover there were no abrupt variations in the PA current when sweeping the input power up and down.
So I looked at the drain waveform and PA power supply ripple during a two tone test with around 20 dBm out:

yellow trace is the drain waveform and cyan trace is the supply ripple: the drain voltage envelope has a small dip at the top which matches "nicely" with the ripple on the PA supply. Changing the input power I saw that there is less ripple at higher (and lower) power output...

Looking at the waveform on the DC/DC converter switching node (U8, pin 7) one can sometimes see this nice waveform

and sometimes this not-so-nice

which seen on a larger timescale gives this

where it can be seen that the glitches on the switching node change in amplitude following the output voltage (current) envelope. Maybe the glitches are due to the converter going in and out discontinuous mode ? Did not try yet to experiment with the capacitor on the feedback divider to see if it makes a difference.

Adding a load resistor to draw some 100 mA more from the converter cleans up the waveforms (and IMD behavior) nicely.

In the measurements above the PA driver was powered but not used so it did not draw much current; in the normal usage it will draw more current and so shift the IMD hump towards lower output powers (cfr the graph here).

In practice all this will not really be an issue but it's interesting to see how the DC/DC converter can influence the PA intermodulation.

73 de Claudio, IN3OTD / DK1CG

[Alan Hopper]

Hi Claudio,
I wonder how well puresignal (or harmonic cancellation) will cope with this source of IMD, my gut feeling is that it could be tricky.  As you say it may not be an issue in real use but It would be interesting to test HL2 with puresignal.

73 Alan M0NNB

[in3otd]

Hello Alan,
I was also wondering if PureSIgnal would be able to correct that but I did never tried to actually use it; BTW, is there a SW running on Linux supporting puresignal? I (very) briefly tried pihpsdr but did not see it there.
OTOH, the measurements show that one could maybe play with a "PureSupply", modulating the drain voltage to reduce the IMD. Oh, maybe that's part of what EER does, hi.

73 de Claudio, IN3OTD / DK1CG

[Alan Hopper]

Hi Claudio,

I don't know of any Linux PureSignal SW, I know it is on John Melton's todo list for pihpsdr but am not aware that he has done it yet. 

73 Alan M0NNB

[in3otd]

Hello Alan,
I've tried PureSignal using PowerSDR, it took some time to have it working and still I'm not sure what's the correct procedure to set it up correctly even after looking at the PowerSDR documentation and WDSP Guide, hi. One thing that I had to change is the "SetPk" value, which as the Guide says has a default of 0.4072 but I had to change it to 0.2 to see the PureSignal correction; the "GetPk" parameter never goes above 0.19 not sure if this is correct or should go up to 0.4.
In any case, with a two-tone output at 37 dBm PEP the IM3 is about -50 dBc with Puresignal (around -35 dBc without). Lowering the drive level is not enough to go to the output levels where the IM3 misbehaves, the audio output level to the H-L should also be lowered but AFAIU it's fixed at max for the two-tone generator in PowerSDR.

73 de Claudio, IN3OTD / DK1CG

[Steve Haynal]

Hi Claudio,

Thanks for testing this. I'll go with whatever you think is best for the bias impedance. Please let me know if you recommend any changes to the schematic, beta3 version.

73,

Steve

KF7O