Cannot fetch and build flcli/libfpgalink

[9868m...@gmail.com]

I'm a newcomer to FPGA and I want to transfer data between PC and FPGA board. I have a Nexys2 board.

I followed the instructions on https://gist.github.com/makestuff/7829484, everything was fine before "fetch and build flcli", after the command "msget.sh makestuff/flcli/20140330", I got an error "fetch of makestuff/flcli/20140330 failed. Are you sure it exists on Github?"

I have also tried many different branches, like libfpgalink, but also got the same error.

Another thing I tried was download libfpgalink-master branch manually from Github, and go the directory where the Makefile locates, but after the commnad "make deps" gives an error:

"No rule to make target 'deps'. Stop".

Could anyone help me with this issue? Thanks.

[Chris McClelland]

Are you by any chance trying to run this in a corporate environment, with an HTTP proxy in place? That, or a temporary outage at GitHub, is the only explanation I can think of for that behaviour. You can debug it easily enough though: look at line 76 of msget.sh. It has a wget of a GitHub resource. Try it explicitly, on the command-line, replacing the environment vars, and without the "-q" (quiet) option:

wget --no-check-certificate https://github.com/makestuff/flcli/archive/20140330.tar.gz

That way, you'll probably see what the error is. If it's a proxy problem, you'll need to set http_proxy and/or https_proxy. See here: https://stackoverflow.com/questions/11211705/setting-proxy-in-wget

Lastly, please use the most recent release, not that old one. The most recent is 20170708. I just updated the gist: https://gist.github.com/makestuff/7829484

Chris

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[Chris McClelland]

Another possibility is you're building on Windows, and you have a firewall preventing wget from accessing GitHub. I'm no Windows expert so I have no idea how to tell your firewall not to do that, but that's what you'll need to do.

On 8 March 2018 at 08:01, Chris McClelland <proph...@gmail.com> wrote:

Are you by any chance trying to run this in a corporate environment, with an HTTP proxy in place? That, or a temporary outage at GitHub, is the only explanation I can think of for that behaviour. You can debug it easily enough though: look at line 76 of msget.sh. It has a wget of a GitHub resource. Try it explicitly, on the command-line, replacing the environment vars, and without the "-q" (quiet) option:

wget --no-check-certificate https://github.com/makestuff/flcli/archive/20140330.tar.gz

That way, you'll probably see what the error is. If it's a proxy problem, you'll need to set http_proxy and/or https_proxy. See here: https://stackoverflow.com/questions/11211705/setting-proxy-in-wget

Lastly, please use the most recent release, not that old one. The most recent is 20170708. I just updated the gist: https://gist.github.com/makestuff/7829484

Chris

On 7 March 2018 at 23:14, 9868m...@gmail.com <9868m...@gmail.com> wrote:

I'm a newcomer to FPGA and I want to transfer data between PC and FPGA board. I have a Nexys2 board.

I followed the instructions on https://gist.github.com/makestuff/7829484, everything was fine before "fetch and build flcli", after the command "msget.sh makestuff/flcli/20140330", I got an error "fetch of makestuff/flcli/20140330 failed. Are you sure it exists on Github?"

I have also tried many different branches, like libfpgalink, but also got the same error.

Another thing I tried was download libfpgalink-master branch manually from Github, and go the directory where the Makefile locates, but after the commnad "make deps" gives an error:

"No rule to make target 'deps'. Stop".

Could anyone help me with this issue? Thanks.

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[9868m...@gmail.com]

Hi Chris,

Thanks a lot for your quick reply. I am building on Windows. 

I ran the command you suggest and got the error: 

"OpenSSL: error:1407742E:SSL routines:SSL23_GET_SERVER_HELLO:tlsv1 alert protocol version. Unable to establish SSL connection." 

I googled this error and it seems like the wget version issue. I check the version of wget in the shell-prompt linked with the shortcut, and it's : GNU Wget 1.12 built on msys." I then downloaded a newer version of wget (1.19) to my computer, but it seems that the wget version in that shell-prompt was not updated, it's still 1.12 and I checked the wget version in the cmd terminal of my computer, it had already been updated to "GNU Wget 1.19.4 built on mingw32.". I tried the "wget --no-check..." command in the cmd terminal and it succeeded. 

So I'm wondering how can I update the wget version in the shell-prompt? Or can I run all the commands in the cmd terminal of my own computer? Thanks.

On Thursday, March 8, 2018 at 2:04:25 AM UTC-6, Chris McClelland wrote:

Another possibility is you're building on Windows, and you have a firewall preventing wget from accessing GitHub. I'm no Windows expert so I have no idea how to tell your firewall not to do that, but that's what you'll need to do.

On 8 March 2018 at 08:01, Chris McClelland <proph...@gmail.com> wrote:

Are you by any chance trying to run this in a corporate environment, with an HTTP proxy in place? That, or a temporary outage at GitHub, is the only explanation I can think of for that behaviour. You can debug it easily enough though: look at line 76 of msget.sh. It has a wget of a GitHub resource. Try it explicitly, on the command-line, replacing the environment vars, and without the "-q" (quiet) option:

wget --no-check-certificate https://github.com/makestuff/flcli/archive/20140330.tar.gz

That way, you'll probably see what the error is. If it's a proxy problem, you'll need to set http_proxy and/or https_proxy. See here: https://stackoverflow.com/questions/11211705/setting-proxy-in-wget

Lastly, please use the most recent release, not that old one. The most recent is 20170708. I just updated the gist: https://gist.github.com/makestuff/7829484

Chris

On 7 March 2018 at 23:14, 9868m...@gmail.com <9868m...@gmail.com> wrote:

I'm a newcomer to FPGA and I want to transfer data between PC and FPGA board. I have a Nexys2 board.

I followed the instructions on https://gist.github.com/makestuff/7829484, everything was fine before "fetch and build flcli", after the command "msget.sh makestuff/flcli/20140330", I got an error "fetch of makestuff/flcli/20140330 failed. Are you sure it exists on Github?"

I have also tried many different branches, like libfpgalink, but also got the same error.

Another thing I tried was download libfpgalink-master branch manually from Github, and go the directory where the Makefile locates, but after the commnad "make deps" gives an error:

"No rule to make target 'deps'. Stop".

Could anyone help me with this issue? Thanks.

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[Chris McClelland]

OK, can you delete (or rename) C:\makestuff, and try again with this one:

https://www.dropbox.com/s/dth1v84nxqddybd/makestuff-windows-20180311.zip

No need to re-run setup.exe, just restart the console.

Chris

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[9868m...@gmail.com]

Hi Chris,

Thank you for the information. I successfully fetch and build flcli. 

Then I tried to fetch and build the VHDL version of cksum example as the tutorial suggested. I have got the hdlmake folder, but I got an error when I ran the command:"../bin/hdlmake.py -g makestuff/swled".

The error appears at "File "c:\Python27\lib\urllib2.py", line 1184, in do_open, raise URLError(err)

urllib2.URLError:<urlopen error [Errno 1] _ssl.c:507: error: 1407742E:SSL routines:SSL23_GET_SERVER_HELLO:tlsv1 alert protocol version>".

And I found a guy who has the similar issue at https://stackoverflow.com/questions/33972671/downloading-https-pages-with-urllib-error14077438ssl-routinesssl23-get-serve

he seems to update the Python and modify his code. But I guess I am not supposed to change the hdlmake.py code, right? Do you have any idea on how to solve this? Thanks!

[Chris McClelland]

You're a patient person! Thanks for your perseverance!

It seems the version of Python the quickstart told you to install is too old to work properly on your system. So...

1) Go to "Control Panel/Programs/Programs and Features" and uninstall Python and PyYAML.

2) Re-install these versions:

https://www.python.org/ftp/python/2.7.14/python-2.7.14.amd64.msi
http://pyyaml.org/download/pyyaml/PyYAML-3.12.win-amd64-py2.7.exe

3) Close any console windows

4) Re-run the desktop shortcut to start a new console, then do this:

cd $HOME/hdlmake
rm bin/hdlmake.py
wget --no-check-certificate -qO bin/hdlmake.py https://raw.githubusercontent.com/makestuff/hdlmake/dev/bin/hdlmake.py
cd apps
../bin/hdlmake.py -g makestuff/swled

If that works OK, you should be able to continue with the quickstart from the line following. Let me know if it works, because if it does I'll push out a new release and update all the quickstarts.

Chris

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[9868m...@gmail.com]

Hi Chris,

Thanks a lot! After updating Python and PyYAML, I can fetch and build the cksum example. 

I got an error when I tried to load FPGALink firmware into Nexys 2:"flOpen(): usbOpenDevice(): LIBUSB_ERROR_NOT_SUPPORTED". 

Before I ran the command, the power light on the board was on, but after running this command, the power light was off and the board couldn't be detected by the computer anymore. Is there any problem with the driver? But I think I have run the zadig.sh command previously. 

BTW, I have another side question, since I have run zadig.sh command, so the original driver has been replaced, right? Since I tried to use the Digilent Adept software to download the .bit file to the board, the Adept cannot detect the device. I read the FPGALink user manual; for FPGALink, we program the board using the command: ./<PLATFORM>/rel/flcli -v <VID:PID>  -i <VID:PID> \ -s -x gen_csvf/ex_cksum_<BOARD>_<PROTOCOL>_vhdl.csvf, correct? So my question is, if I want to try the GUI option (Adept) to program the board, how can I revert back to the original driver? Thanks.

[Chris McClelland]

The first time you try the firmware-load ("flcli -v 1d50:602b:0002 -i 1443:0005"), the console will hang there, and Windows will detect the newly-reconfigured device (1d50:602b). You'll need to run zadig.sh again in order to install a driver for that device. Once the driver is installed, you can unplug your nexys2, plug it in again, and re-run the firmware load command, whereupon it will work (because Windows now has a driver for the new firmware). If it doesn't work for you, please report exactly what happens in explicit detail, step by step, listing the exact commands you type and what happens as a result.

It is possible to switch back and forth between Digilent Adept and FPGALink, but not easily. You would need to cut a track on the nexys2 PCB and solder a jumper to the board. With the jumper shorted, the device will show up in Adept. With the jumper open-circuit, it will be available for use by FPGALink. I can show you how to do this if you're interested. If you don't want to do that, the only way to switch back to Adept is to uninstall the FPGALink driver and reinstall the Adept driver.

You should trust the quickstart more than the user manual, which is horribly out of date. For example, to connect to the board (once firmware is installed), enable the FPGA's power and then program the FPGA, you do "flcli -v 1d50:602b:0002 -d D7+ -p J:D0D2D3D4:fpga.xsvf".

Chris

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[9868m...@gmail.com]

Hi Chris,

Thanks for your reply! 

I have successfully built the VHDL version of the cksum example using the command: "../../../../../bin/hdlmake.py -t ../../templates/fx2all/vhdl -b nexys2-500 -p fpga". (I'm using a Nexys2-500 board)

Then I type the command:"../../../../../../apps/flcli/msvc.x64/rel/flcli -v 1d50:602b:0002 -i 1443:0005", and I got the message:

"Attempting to open connection to FPGALink device 1d50:602b:0002...". 

"Loading firmware into 1443:0005..."

"Awaiting renumeration..."

"Attempting to open connection to FPGALink device 1d50:602b:0002 again..."

"flOpen():usbOpenDevice(): LIBUSB_ERROR_NOT_SUPPORTED"

After this command the power light on the board was off, and the device disappeared from the computer. But after I unplug and plug the usb again, the power light turned on again. Thanks.

[Chris McClelland]

Did you install a driver using zadig for both 1443:0005 and 1d50:602b?

On 15 March 2018 at 21:58, 9868m...@gmail.com <9868m...@gmail.com> wrote:

Hi Chris,

[9868m...@gmail.com]

Hi Chris,

It seems that I didn't install the driver for both, after I installed the driver for FPGALink device, that error was gone. Thanks for your help!

But it seems there is some issue in programming the board. I ran the command: "../../../../../../apps/flcli/msvc.x64/rel/flcli -v 1d50:602b:0002 -d D7+ -p J:D0D2D3D4:fpga.xsvf" and got a message saying:

"flProgram(): jProgram(): csvfplay(): XSDRTDO failed: 

Got: 0000000000 

Mask: FEFFFF1F00 

Expecting: 264184E301" 

Please see the attached file for the detailed message. Thanks.

[Chris McClelland]

That probably means you've got the "USB" jumper missing from the "Power Select" block, near the top left of the board.

If that jumper is present, try running flcli with -d D7+ to power on the FPGA first; you should see the power LED come on.

Then, run flcli again with the -p J:D0D2D3D4:fpga.xsvf to attempt to program the FPGA.

Chris

On 16 March 2018 at 00:56, 9868m...@gmail.com <9868m...@gmail.com> wrote:

Hi Chris,

It seems that I didn't install the driver for both, after I installed the driver for FPGALink device, that error was gone. Thanks for your help!

But it seems there is some issue in programming the board. I ran the command: "../../../../../../apps/flcli/msvc.x64/rel/flcli -v 1d50:602b:0002 -d D7+ -p J:D0D2D3D4:fpga.xsvf" and got a message saying:

"flProgram(): jProgram(): csvfplay(): XSDRTDO failed: 

Got: 0000000000 

Mask: FEFFFF1F00 

Expecting: 264184E301" 

Please see the attached file for the detailed message. Thanks.

On Thursday, March 15, 2018 at 5:36:29 PM UTC-5, Chris McClelland wrote:

Did you install a driver using zadig for both 1443:0005 and 1d50:602b?

On 15 March 2018 at 21:58, 9868m...@gmail.com <9868m...@gmail.com> wrote:

Hi Chris,

Thanks for your reply! 

I have successfully built the VHDL version of the cksum example using the command: "../../../../../bin/hdlmake.py -t ../../templates/fx2all/vhdl -b nexys2-500 -p fpga". (I'm using a Nexys2-500 board)

Then I type the command:"../../../../../../apps/flcli/msvc.x64/rel/flcli -v 1d50:602b:0002 -i 1443:0005", and I got the message:

"Attempting to open connection to FPGALink device 1d50:602b:0002...". 

"Loading firmware into 1443:0005..."

"Awaiting renumeration..."

"Attempting to open connection to FPGALink device 1d50:602b:0002 again..."

"flOpen():usbOpenDevice(): LIBUSB_ERROR_NOT_SUPPORTED"

After this command the power light on the board was off, and the device disappeared from the computer. But after I unplug and plug the usb again, the power light turned on again. Thanks.

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[9868m...@gmail.com]

Hi Chris,

Thank you very much for your information. Now I can successfully complete the cksum example. But I am still not quite clear about how this FPGALink firmware works. 

1. If I want to build my own applications, which folder/files shall I modify and start from? If I want to program the board with my own application, I need to start from the step "# Fetch and build the VHDL version of the cksum example: ../../../../../bin/hdlmake.py -t ../../templates/fx2all/vhdl -b nexys2-1200 -p fpga" in the quickstart tutorial, right? But do I need to load FPGALink firmware and run "zadig.sh" every time to program the board? Can I directly program the FPGA after the above command? Thanks.

2. The task I want to accomplish using this FPGA board is building a light-weight demo system for an ASIC chip. I need to generate some digital test patterns using this board, for example, scan clks, scan data and some other digital signals with proper timing. I have already prepared the data pattern in .txt (.dat) files. I want to transfer the data pattern in the files to the board and output them from different digital output ports on the FPGA board to my ASIC chip. The difficult part is that I have scan chains in my ASIC chip and I need to repeat the scan multiple times (>100) to properly program the chip. If I generate the complete pattern beforehand, there would be several mega bits of data in the file, and I'm afraid there's not enough registers/on-chip block RAM available on the board. 

So I think I have two options, 1) I should store the entire data pattern in the external RAM (16MB from Micron) and send it to the board and finally send it out sequentially to the ASIC chip; 2) each time I only send 1 scan pattern to the registers on the board and program the FPGA multiple times to finish this task (each time the scan pattern is different). Or is it possible to send the different data files multiple times to FPGA without programming the board every time? (If this is possible, please ignore the next two questions.) 

I have questions for both options, for option 1: is it possible for FPGALink to write some data into the external RAM on the Nexys2 board? I think in the FPGALink examples, PC is writing some files to the registers on board, so I think option 2 might be more easier to implement using FPGALink. 

For option 2, if I need to program the board multiple times (>100) using for loop, how can I do this efficiently? Since I need to repeat this >100 times, it's not reasonable to manually do this. I can generate the data pattern/read the data pattern in C or Python, but I don't know how to program the board in C/Python after I have prepared the data pattern and repeat this continuously in the code. I'm not very familiar with API or DLL. Or can I use a for loop in the shell script to program the FPGA multiple times?

I'm sorry, I have so many questions. Could you please point me to some similar examples in FPGALink so that I can start from? Thanks a lot!

3. I am also wondering can I use PMOD modules, like A\D converters available from Digilent in FPGALink? 

Thank you very much!!!

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[Chris McClelland]

1) Let's call c:/makestuff "$HOME".

First, the software. In $HOME/libs, there's a bunch of C libraries (for you, DLLs), including libfpgalink, which is the library you need on the software side to talk to an FPGALink device. In $HOME/apps, there's an example application called "flcli", which uses the libfpgalink library. To do its stuff. There are also some examples in various languages under $HOME/libs/libfpgalink/examples.

Now, the FPGA stuff. You have in $HOME/hdlmake/libs/makestuff a bunch of FPGA libraries, including comm-fpga, which is the library you need on the FPGA side in order to talk to your FPGALink software. You have in $HOME/hdlmake/apps/makestuff the "switches & leds application", an example to get you started. Since you're working with a nexys2-500 board, and presumably with VHDL rather than Verilog, and if you only care about the "cksum" example (and not the "fifo" example), you only need to worry about these files:

swled
├── README
├── COPYING
├── COPYING.LESSER
├── cksum
│   └── vhdl
│       ├── README
│       ├── hdlmake.cfg
│       └── cksum_rtl.vhdl
└── templates
    ├── fx2all
    │   ├── boards
    │   │   └── nexys2-500
    │   │       ├── board.cfg
    │   │       ├── board.ucf
    │   │       ├── board.ut
    │   │       ├── board.xst
    │   │       ├── fpga.batch
    │   │       └── prom.batch
    │   └── vhdl
    │       ├── hdlmake.cfg
    │       └── top_level.vhdl
    └── harness.vhdl

Because this example has to work with a variety of boards, and several different FPGALink comm-fpga implementations, the example directory itself (swled/cksum/vhdl) doesn't have the top-level VHDL file: that is in templates/fx2all/vhdl. The hdlmake.py script knows how to pull everything together by looking at the hdlmake.cfg files (which are just YAML text files). If you don't care about supporting other boards, you could just move the top_level.vhdl and harness.vhdl files alongside cksum_rtl.vhdl, and delete the templates/fx2all/vhdl directory altogether, to make it simpler. You could look at the "blinky" example (cd $HOME/hdlmake/apps; ../bin/hdlmake.py -g makestuff/blinky) for a more straightforward example.

2) Why not sidestep the external memory altogether and just pipe the data straight from the USB interface into your ASIC? If not, you could just buffer the data you send over FPGALink in the external RAM on the Nexys2 board (there's a basic memory-controller for it here: https://github.com/makestuff/umdkv2/blob/legacy/vhdl/MemoryController.vhdl).

Either way, you certainly don't need to reprogram the FPGA in order to transfer your test-patterns to the FPGA. FPGALink has two main functions: programming and communication. They are logically separate. Once you've programmed the FPGA, you can then communicate your test-patterns to it. If you're not familiar with writing software, I recommend getting a Python book and playing with the Python examples.

3) Of course, they're just bits of hardware. The Nexys2 master .ucf file from Digilent has the pin mappings for each of the PMOD ports.

Lastly, I can't stress enough how important it is to experiment. Take the existing code and modify it, learn how to use the hdlmake.py script to build your modified code. Study the hdlmake.cfg files. Try the Python examples. Write your own loops and stuff that send stuff to the FPGA and retrieve data back.

Chris

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[Chris McClelland]

Ooops, sorry forgot to answer the "zadig/firmware" question:

Zadig installs a driver on Windows. You only need to do that once (actually twice, once for 1443:0005 and again for 1d50:602b) when you want to run your code on a new Windows PC.

You need to do the firmware-load step whenever you disconnect and reconnect your Nexys2 from your PC (the onboard FX2 microcontroller forgets its firmware when you disconnect it from your PC, and loads the default Digilent firmware from EEPROM when you reconnect it).

[9868m...@gmail.com]

Hi Chris,

Thank you very much for your detailed explanation! Now I have a better idea! 

I would prefer pipe the data directly from USB. I found a C example from "c:\makestuff\libs\libfpgalink\examples\c", so I need to modify "main.c" to implement my own application. From README file, there's instruction about how to call FPGALINK from C, and I am not exactly sure what does the command:"dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=16" means. It seems that it specify the path of foo.dat. But I couldn't find the directory "dev/urandom". What does "dd" "if" "of" "bs" "count" mean exactly? 

And it seems I cannot view the foo.dat file, so I'm wondering what the data format should this file be or how can I view the content of this file? 

From the code, I know that flWriteChannelAsync() function buffers up to 64KiB of data, is 64KiB limit for each channel or all channels together? And does flWriteChannel() has the same limit?

If I use C/Python to call FPGALink, can I also use flcli? 

Thanks a lot!

[Chris McClelland]

It means "copy 16 blocks of 64KiB from /dev/urandom to a file /var/tmp/foo/dat" (see [1]). The /dev/urandom thing is not a file, it's a source of pseudorandom bytes on Unix-like systems. It should still work for you, despite the fact that you're on Windows. Failing that, any old file will do - you're just piping data into the FPGA to verify that the FPGA calculates the same checksum that the software does. The actual content of the file doesn't matter in the least.

What makes you think flWriteChannelAsync() has a block-size limit? It's been a few years since I looked at that code, but it doesn't look like there's any such limit, to me.

If you write a custom application in C or Python, you can still use flcli, but only one application can have an FPGALink device open at any given time.

Chris

[1]https://en.wikipedia.org/wiki/Dd_(Unix)

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