Re: [fpgalink-users] Basys2

[Chris McClelland]

Hi Diogo,

FPGALink supports AVR-based designs like the Basys2. It works well, but
rather slower than the FX2-based boards (it gives about 330KiB/s
compared to 43MiB/s with the FX2). The tricky part is it involves
installation of new firmware on your board, a process which (due to how
the board has been designed) is not straightforward, and not without
some risk to your board, so it's not something I can really recommend
for beginners. If you wish to go ahead and install it anyway, let me
know and I'll show you how.

Chris


On Wed, 2012-08-29 at 16:11 -0700, Diogo Primor wrote:
> Hello everyone,
>
>
> I wonder if anyone has experienced in basys2? I am a new user =S
>
>
> Tks
>
>
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[Diogo Primor]

Hi Chris,

thanks for the help, it will be easier to use the CY7C68013A and thus gives all fpga's ? because this device is relatively inexpensive and easy to find (... on ebay) ?

Tks

Diogo

2012/8/30 Chris McClelland <fpgal...@m3.ath.cx>

--
Cumprimentos,
Diogo Primor

[Chris McClelland]

You mean buy an external CY7C68013A board and wire it up to your
Basys2's external I/Os?

You could certainly do that. Remove the 3.3V regulator from the
CY7C68013A board and then connect the 15 signal lines (described in
section 4.2 of the manual) plus GND and 3.3V between the two boards. You
can connect the four JTAG lines too if you want to program the FPGA
through FPGALink.

That solution would give you better throughput, but it will use up some
of your external I/O, and it's probably at a similar level of difficulty
to installing the FPGALink AVR firmware directly on your board.

Perhaps it would be better if I described the steps to load new AVR
firmware:

1) Install a design into the Basys2 FPGA that will connect one of the
Basys2 buttons to the USB-DB7 line on the AVR. This allows you to
control the AVR's hardware bootloader (HWB) input.

2) Find J4 (the JTAG connector) on your Basys2 and attach a momentary
switch between pin 1 & 5. This allows you to control the AVR's RESET
input.

3) Connect the board to your computer.

4) Press (& hold) RESET

5) Press (& hold) HWB

6) Release RESET

7) Release HWB

That should start the hardware bootloader, which will enumerate on your
computer as 03eb:2ffa. You should then be able to use Atmel FLIP (on
Windows) or dfu-programmer (on Linux & MacOSX) to save the existing
firmware and load new firmware. Since your board's AVR has an 8MHz
crystal you will need to change the F_CPU value to 8000000 before
building the firmware[1].

Naturally, this will invalidate your warranty and I can accept no
liability for damage to your board (but I will try to help you recover
if something does go wrong).

Chris

[1]https://github.com/makestuff/libfpgalink/blob/master/firmware/avr/Makefile#L80

[Chris McClelland]

Interesting. Can you confirm that the AVR bootloader does not start (i.e
you do not get device 03eb:2ffa) when you follow my instructions below?
Have you verified that the HWB and RESET lines do actually toggle as
expected when you press your buttons?

If it turns out that you are correct and the 4KiB factroy bootloader has
been erased by Digilent, then the only way to install the FPGALink
firmware will be to program it using an external programmer. If you want
to proceed with this approach, send me a private email with your postal
address and I'll send you a suitable USB programmer[1].

The Basys2's J4 connector has the following connections, which are
exactly those needed by the external programmer:

Pin Function
1 RESET
2 MOSI
3 MISO
4 SCLK
5 GND
6 +3.3V

You *may* be able to backup the existing firmware from the device using
this method. It's possible Digilent have protected it though, in which
case putting the FPGALink firmware on the board will be an irreversible
operation, so you'll never be able to use Adept2 with it again unless
you somehow get hold of the firmware binary from a different source.

Alternatively, if you want to proceed with the Adept reverse-engineering
approach, some research I did before beginning work on FPGALink may be
useful to you[2][3]. Unfortunately it only covers the EPP operation, not
JTAG. Reverse-engineering the JTAG operations proved too difficult.
Personally I consider the reverse-engineering approach to be a dead-end,
so I can't help further with it.

Chris


[1]http://www.makestuff.eu/wordpress/minimus-avr-isp-clone/
[2]http://www.makestuff.eu/wordpress/software/digilent-nexys2-epp-utility/
[3]http://www.makestuff.eu/wordpress/enabling-linux-usb-debugging/




On Wed, 2013-02-20 at 05:50 -0800, xgdl...@gmail.com wrote:
> I am interested in Basys2 too. I use your method, but basys2 still
> can't run in ISP Mode.
> May be digilent erase the bootloader which can expose it's firmware.
> Someone have other method to get at90usb162's firmware. Reverse
> engineering the host
> tool Adept seems to be easier.
>
>
> 在 2012年8月30日星期四UTC+8下午6时25分27秒，Chris McClelland写道：

> You received this message because you are subscribed to the "FPGALink
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[Altynbek Isabekov]

Hi to all.

In response to: 

On Wednesday, 20 February 2013 16:25:18 UTC+2, Chris McClelland wrote:

You *may* be able to backup the existing firmware from the device using 
this method. It's possible Digilent have protected it though, in which 
case putting the FPGALink firmware on the board will be an irreversible 
operation, so you'll never be able to use Adept2 with it again unless 
you somehow get hold of the firmware binary from a different source. 

Chris 

 

Just to confirm, Basys2's AT90USB162 microcontroller's firmware is protected against unauthorized access and copying.

I was about to flash the Basys2 board with the NeroJTAG firmware using J4 connector, but as a precaution I wanted to backup the original Digilent firmware.

Unfortunately, I couldn't do it. The lock bits have a value of "3C" in hexadecimal, which is "0011 1100" in binary.

These two bytes correspond to

"unused, unused, BLB12, BLB11, BLB02, BLB01, LB2, LB1" bits described in the "Program And Data Memory Lock Bits" section of the uC's datasheet.

I believe that LB2 = 0, LB1 = 0 means that "Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode."

So flashing with NeroJTAG firmware is a one way ticket.

Also, the fuse bits information is given below:

avrdude: Version 6.1, (openSUSE Buildservice)

         Copyright (c) 2000-2005 Brian Dean, http://www.bdmicro.com/

         Copyright (c) 2007-2014 Joerg Wunsch

         System wide configuration file is "/etc/avrdude.conf"

         User configuration file is "/home/johndoe/.avrduderc"

         User configuration file does not exist or is not a regular file, skipping

         Using Port                    : usb

         Using Programmer              : usbasp

         AVR Part                      : AT90USB162

         Chip Erase delay              : 9000 us

         PAGEL                         : PD7

         BS2                           : PC6

         RESET disposition             : possible i/o

         RETRY pulse                   : SCK

         serial program mode           : yes

         parallel program mode         : yes

         Timeout                       : 200

         StabDelay                     : 100

         CmdexeDelay                   : 25

         SyncLoops                     : 32

         ByteDelay                     : 0

         PollIndex                     : 3

         PollValue                     : 0x53

         Memory Detail                 :

                                  Block Poll               Page                       Polled

           Memory Type Mode Delay Size  Indx Paged  Size   Size #Pages MinW  MaxW   ReadBack

           ----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------

           eeprom        65    20     4    0 no        512    4    128  9000  9000 0x00 0x00

           flash         65     6   128    0 yes     16384  128    128  4500  4500 0x00 0x00

           lfuse          0     0     0    0 no          1    0      0  9000  9000 0x00 0x00

           hfuse          0     0     0    0 no          1    0      0  9000  9000 0x00 0x00

           efuse          0     0     0    0 no          1    0      0  9000  9000 0x00 0x00

           lock           0     0     0    0 no          1    0      0  9000  9000 0x00 0x00

           calibration    0     0     0    0 no          1    0      0     0     0 0x00 0x00

           signature      0     0     0    0 no          3    0      0     0     0 0x00 0x00

         Programmer Type : usbasp

         Description     : USBasp, http://www.fischl.de/usbasp/

avrdude: auto set sck period (because given equals null)

avrdude: AVR device initialized and ready to accept instructions

Reading | ################################################## | 100% 0.02s

avrdude: Device signature = 0x1e9482

avrdude: safemode: lfuse reads as DE

avrdude: safemode: hfuse reads as D9

avrdude: safemode: efuse reads as FC

avrdude: safemode: lfuse reads as DE

avrdude: safemode: hfuse reads as D9

avrdude: safemode: efuse reads as FC

avrdude: safemode: Fuses OK (E:FC, H:D9, L:DE)

avrdude done.  Thank you.

[Chris McClelland]

Thanks for confirming, Altynbek. I guess the only other solution if you want reversibility is to desolder the AT90USB162 and replace it with a fresh chip, if your rework skills are up to it (mine certainly aren't).

If you do want to go the one-way ticket, the FPGALink AVR firmware is pretty stable, I've used it in several projects.

Chris

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[Chris McClelland]

Altynbek,

BTW, congratulations, you're the 200th member of the FPGALink user group!

:-)

[Altynbek Isabekov]

That's awesome! I'm #200.
In the scope of the university project we will try to design our own Xilinx development board with AT90USB162 flashed with NeroJTAG as a JTAG controller, so desoldering tiny SMD components from the Basys2 board won't be necessary. Thanks for the FPGALink documentation.

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Sincerely yours, Altynbek

[Chris McClelland]

Awesome!

You could use this KiCad design to guide you: https://github.com/makestuff/lx9/tree/r3

TBH the FX2 chip which this board uses is much better than the AVR, and only $1 or $2 more expensive. Its throughput is 42MiB/s compared to the AVR's ~330KiB/s, so if you're making your own board using unmodified FPGALink firmware it makes sense to use it instead.

The only reasons why you might want to stick with the AVR are:

1) You want to customise the firmware - this is easy and fun on the AVR but the FX2 is pretty horrible from a programmer's point of view.

or

2) You want to minimise the number of FPGA I/Os used for the host interface. The FX2 needs 15 I/Os. The AVR in EPP mode needs only 12 I/Os; in sync-serial mode it needs only three I/Os.

Chris

[Altynbek Isabekov]

Thanks for the guidance.
It seems that switching from the familiar AVR architecture to a new CY7C68013 is worth gained performance boost.

We will definitely try it.

[Altynbek Isabekov]

Hi, Chris. I want to test FPGAlink on the Digilent Basys2 board (www.digilentinc.com/basys2/).

Just to be sure, can you confirm that flashing the Basys2 board with NeroJTAG or HackAVR firmware gives successful results? Does FPGAlink recognize the board?

As I understood, in order to flash it I have to use the JTAG-SPI interface (header J4) on the board and follow the AVR's hardware bootloader (HWB) method described above.

Thanks.

[Chris McClelland]

I originally designed the AVR firmware to work with the Basys2 (I don't own a Basys2, so I used an AVR board connected to a separate FPGA, mimicking the Basys2's connections for JTAG & EPP), but so far as I'm aware it has never been tested on an actual Basys2. If you give me a day or so I'll check over the firmware and the Basys2 schematic, and verify that it's correct, because I have not looked at the Basys2 support for several years.

Chris 

[Altynbek Isabekov]

That would be awesome!

[Onurhan Öztürk]

Hello, I am a new member and I wonder about the same thing with Altynbek. Is there anything new? Can you verify that Basys2 wiring is compatible with FPGALink?

Thanks

Onurhan

[Peter Stuge]

Onurhan Öztürk wrote:
> Hello, I am a new member and I wonder about the same thing with Altynbek.

Hi and welcome!

> Is there anything new? Can you verify that Basys2 wiring is compatible
> with FPGALink?

No email in the thread so probably no news. In order to offload Chris
a bit you could also check the schematics yourself. Look at schematic
and/or source code for the AVR programmer that Chris has documented
and compare that with the Basys2 schematic.


//Peter

[Chris McClelland]

Sorry guys, last week whilst I was away from home, my laptop broke and I was unable to do anything.

It looks to me like the connections in the Basys2 schematic are already correct in the "minimus" Board Support Package of the AVR firmware. So you just need to make a new BSP, based on "minimus"; it looks like the only thing you need to change is the clock frequency, from 16000000 to 8000000.

You will also need to create a new template for the cksum example, to set the correct pin constraints and FPGA type.

Please send me a pull request for these two when you have it working, and then it'll be available for others to use.

The overall process will look something like this:

https://gist.github.com/makestuff/74449db9fd9cce2d36d9

Once things work nicely you might want to add some custom init code to the basys2's firmware BSP to automatically power up the FPGA by setting PC2 high (see iceblink.c for example).

Let me know how you get on...

Chris

[Chris McClelland]

BTW, I think the first firmware load needs to be done with an external programmer connected to the Basys2 board. You can either do this directly with avrdude, or you can use avrdude to install the LUFA DFU bootloader:

$ cd ${HOME}/20150315/makestuff/3rd/LUFA-130901/Bootloaders/DFU
$ make MCU=at90usb162 BOOT_SECTION_SIZE_KB=4 FLASH_SIZE_KB=16
  :
$ avrdude -c avrispmkII -P usb -p at90usb162 -e -U flash:w:BootloaderDFU.hex -U hfuse:w:0xD9:m -U lfuse:w:0x5E:m -U efuse:w:0xF4:m

The board will now power up for the first time in DFU mode, whereupon you can load the firmware using that:

$ lsusb | grep 2ffa
Bus 002 Device 041: ID 03eb:2ffa Atmel Corp.

$ cd ${HOME}/20150315/makestuff/libs/libfpgalink/firmware/avr
$ make BSP=basys2 dfu  # install FPGALink firmware

The advantage of doing it this way is you can then use the "gordon" tool to programmatically put the AVR back in DFU bootloader mode, so subsequent firmware upgrades can be done without the need for an external programmer: you can just run "make BSP=basys2 dfu" in the libfpgalink/firmware/avr directory:

$ # Fetch and build "gordon" tool:

$ cd ${HOME}/20150315/makestuff/apps
$ ../scripts/msget.sh makestuff/gordon
  :
$ cd gordon
$ make deps
  :

$
$ # Use it to put the AVR back in DFU mode:

$ lin.x64/rel/gordon -v 1d50:602b:0001 -b  # put AVR back in DFU mode
$ lsusb | grep 2ffa
Bus 002 Device 041: ID 03eb:2ffa Atmel Corp.

$
$ # Now update the firmware using the DFU bootloader

$ cd ${HOME}/20150315/makestuff/libs/libfpgalink/firmware/avr
$ make BSP=basys2 dfu  # update FPGALink firmware
  :
$

Endless fun!

Chris

[Altynbek Isabekov]

Hi to all. Thanks for the instructions.

I've tested the old NeroJTAG firmware located at https://github.com/makestuff/neroJtag on ATmega16U2 which is used as an ISP programmer on the Arduino board :)

I didn't wire it up to the Basys2 board because there was no access to one of the pins and it's hard to solder a wire to an SMD package. The attached device gets recognized as "NeroJTAG/AVR v1.0" both by Windows and Linux.
The FPGAlink client program "flcli" recognizes the board and gives "Connected to FPGAlink device 03eb:3002" output. However, it turns out that this firmware version does not support CommFPGA protocol. 

So now I'm trying to compile the newest AVR firmware located at https://github.com/makestuff/libfpgalink/tree/master/firmware/avr for our new board prototype based on AT90USB162 with EPP support.

I substituted 

#include STR(boards/BSP.h)

with

#include "minimus.h"

and set the proper MCU model and the clock frequency value.

When I run "make" it gives an error while compiling "bootloader.c":

[joh...@open.SUSE][⋯/avr]% avr-gcc -c -mmcu=at90usb162 -I. -gdwarf-2 -DF_CPU=16000000UL -DF_USB=16000000UL -DBSP=minimus -DUSART_DEBUG=0 -DBOARD=BOARD_BUMBLEB -DARCH=ARCH_AVR8 -D USB_DEVICE_ONLY -D FIXED_CONTROL_ENDPOINT_SIZE=8 -D FIXED_NUM_CONFIGURATIONS=1 -D USE_FLASH_DESCRIPTORS -D USE_STATIC_OPTIONS="(USB_DEVICE_OPT_FULLSPEED | USB_OPT_AUTO_PLL)" -D USB_STREAM_TIMEOUT_MS=1000 -O2 -funsigned-char -funsigned-bitfields -ffunction-sections -fno-inline-small-functions -fpack-struct -fshort-enums -fno-strict-aliasing -Wall -Wstrict-prototypes -Wa,-adhlns=./bootloader.lst -ILUFA-130901 -I../../../../common -std=c99 -MMD -MP -MF .dep/bootloader.o.d  bootloader.c -o bootloader.o

In file included from bootloader.c:13:0:

bootloader.c: In function 'Bootloader_Jump_Check':

bootloader.c:29:25: error: expected ':' or ')' before 'STR'

   __asm volatile("jmp " STR(BOOTLOADER_START_ADDRESS)::);

There is a problem in macro pre-processing. It looks so simple, it just puts some assembly inline code "jmp SOME_ADDRESS" but I cannot figure out how to fix it. Does anybody know how to solve it?

Thanks in advance.

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Sincerely yours, Altynbek

[Chris McClelland]

I gave you a very detailed script to follow:

https://gist.github.com/makestuff/74449db9fd9cce2d36d9

I'm more than happy to help you, but if I give you detailed instructions and you choose not to follow them, then with all due respect, you're on your own.

Chris

[Altynbek Isabekov]

Actually I followed them till the line #12 when "msget.sh" gave an error and couldn't download it. I had to pull the necessary repositories manually. "flcli" was up-to-date, and it turns out that I pulled an old version of the "common" library which contained "makestuff.h" without the STR macro. Also "make BSP=basys2" wasn't working and I had to modify the BSP headers in each file. Eventually I gave up and switched to the NeroJTAG firmware and succeeded to flash the ATmega16U2 board with it.

Anyways, the source of my problems was the "http_proxy" variable in my ZSH. There were some issues with the proxy server. Fetching the correct version (20150315) of the "common" solves the problem and there are no errors during compilation. Now I will continue with the rest. 

Thanks a lot.