ZedBoard Implementation
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Dylan Ismari
Feb 11, 2014, 5:39:54 PM2/11/14
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Hi All.
I have been working on a Co-Design Project with the new Zedboard from Digilent. The board has a zynq-7020 chip on it with a dual-core embedded ARM. I have a hardware implementation in the programming fabric that I would like to speed up via communications over USB (currently, I use minicom and a UART connection).
The host machine runs Red Hat Linux.
I have taken a look at the FPGAlink software but I really have no clue on how to adapt it for this board. I am hoping to just achieve communication where I can send data to the ARM and receive data from it. The ARM should take care of the interaction with the programming fabric. I currently am doing this over the UART.
Thanks!
-Dylan
I have been working on a Co-Design Project with the new Zedboard from Digilent. The board has a zynq-7020 chip on it with a dual-core embedded ARM. I have a hardware implementation in the programming fabric that I would like to speed up via communications over USB (currently, I use minicom and a UART connection).
The host machine runs Red Hat Linux.
I have taken a look at the FPGAlink software but I really have no clue on how to adapt it for this board. I am hoping to just achieve communication where I can send data to the ARM and receive data from it. The ARM should take care of the interaction with the programming fabric. I currently am doing this over the UART.
Thanks!
-Dylan
Chris McClelland
Feb 11, 2014, 7:00:47 PM2/11/14
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Hi Dylan,
FPGALink currently relies on the existance of an intelligent (i.e programmable) USB microcontroller sitting between the host and the FPGA. The Zedboard does not appear to have that. It appears to have a USB-USART bridge (lacking hardware flow-control), a general-purpose OTG transceiver (TUSB1210) and a FTDI for JTAG-programming.
For programming the FPGA your only options are (a) write an FTDI back-end for the FPGALink JTAG code, or (b) use a separate FPGALink JTAG adaptor connected to the Zed's JTAG port (you can get suitable hardware for $5-$10).
For the host<->FPGA communications, you could use the USART port and write a suitable back-end for the CommFPGA functions in the FPGALink library, but the USART interface's hardware flow-control lines are not connected, so it's of limited usefulness. The other option is undoubtedly the best and most elegant, but also the most work: use the TUSB1210 transceiver and implement the CommFPGA protocol in the FPGA. The '1210 is a fully general USB device/host interface though so it will be a lot of work, unless you can find ready-made device-mode VHDL examples implementing vendor-commands and bulk read/write endpoints.
In summary, it's doable, but it's a lot of work. I'm more than happy to help however I can. Good luck!
Chris
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Dylan Ismari
Feb 12, 2014, 11:08:28 AM2/12/14
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Thank you for the reply.
Currently I am using the UART for COMM's. It is just too slow for moving upwards of 70 MB of data per test that we run. The UART really kills any performance limited by the BAUD of the UART.
I see that the board does in fact have this TUSB1210 Chip. It lives right behind the USB OTG port physically but I do not know how it is wired. I am investigating currently if the ARM core has anything that I could leverage. The pads for the USB OTG port live within the realm of the ARM core (not accessible form the Programming Fabric).
Just out of curiosity, do you know of good reference materials on how to set up these drivers? I have been looking on the net for quite some time and to limited success. I was pointed the way of your web-page by an assignment from an university.
Thanks again
-Dylan
Currently I am using the UART for COMM's. It is just too slow for moving upwards of 70 MB of data per test that we run. The UART really kills any performance limited by the BAUD of the UART.
I see that the board does in fact have this TUSB1210 Chip. It lives right behind the USB OTG port physically but I do not know how it is wired. I am investigating currently if the ARM core has anything that I could leverage. The pads for the USB OTG port live within the realm of the ARM core (not accessible form the Programming Fabric).
Just out of curiosity, do you know of good reference materials on how to set up these drivers? I have been looking on the net for quite some time and to limited success. I was pointed the way of your web-page by an assignment from an university.
Thanks again
-Dylan
On Tuesday, February 11, 2014 5:00:47 PM UTC-7, Chris McClelland wrote:
Hi Dylan,FPGALink currently relies on the existance of an intelligent (i.e programmable) USB microcontroller sitting between the host and the FPGA. The Zedboard does not appear to have that. It appears to have a USB-USART bridge (lacking hardware flow-control), a general-purpose OTG transceiver (TUSB1210) and a FTDI for JTAG-programming.For programming the FPGA your only options are (a) write an FTDI back-end for the FPGALink JTAG code, or (b) use a separate FPGALink JTAG adaptor connected to the Zed's JTAG port (you can get suitable hardware for $5-$10).For the host<->FPGA communications, you could use the USART port and write a suitable back-end for the CommFPGA functions in the FPGALink library, but the USART interface's hardware flow-control lines are not connected, so it's of limited usefulness. The other option is undoubtedly the best and most elegant, but also the most work: use the TUSB1210 transceiver and implement the CommFPGA protocol in the FPGA. The '1210 is a fully general USB device/host interface though so it will be a lot of work, unless you can find ready-made device-mode VHDL examples implementing vendor-commands and bulk read/write endpoints.In summary, it's doable, but it's a lot of work. I'm more than happy to help however I can. Good luck!Chris
Hi All.--
I have been working on a Co-Design Project with the new Zedboard from Digilent. The board has a zynq-7020 chip on it with a dual-core embedded ARM. I have a hardware implementation in the programming fabric that I would like to speed up via communications over USB (currently, I use minicom and a UART connection).
The host machine runs Red Hat Linux.
I have taken a look at the FPGAlink software but I really have no clue on how to adapt it for this board. I am hoping to just achieve communication where I can send data to the ARM and receive data from it. The ARM should take care of the interaction with the programming fabric. I currently am doing this over the UART.
Thanks!
-Dylan
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Chris McClelland
Feb 12, 2014, 12:19:17 PM2/12/14
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Hi Dylan,
You may find it useful (if you're not already familiar with USB internals) to refer to this reference on USB:
Before diving into writing code, you should read the TRM and verify that the Zynq architecture supports connecting a pair of HiSpeed bulk endpoints (one IN, one OUT) directly to the PL fabric (i.e no DMA, just direct FIFOs).
There's a discussion about bare-metal USB device config here:
Apparently there is a Xilinx-supplied example that implements the USB Mass-Storage protocol, which is an ideal starting point because in order to get the MSP working you need control and bulk endpoints working, which is also precisely what FPGALink requires.
Once you have the example working (i.e enumerating correctly on your host PC), you can start cutting it down to its bare minimum; basically all you need to start with is a simple vendor command like the "calculator" command I describe here:
You can build the ucm & hxd code on your Ubuntu host like this:
sudo apt-get install build-essential libusb-1.0-0-dev
cd $HOME
mkdir 20140111
cd 20140111
wget -qO- http://makestuff.eu/bil | tar zxf -
cd makestuff/apps
../scripts/msget.sh makestuff/ucm/20140111
cd ucm
make deps
cd ..
../scripts/msget.sh makestuff/hxd
cd hxd
make deps
The "calculator" firmware for the FX2 (using Dennis Muhlestein's fx2lib library) is here, which you need to port to the Zynq controller:
...and here's the same code for the Atmel AVR (using Dean Camera's LUFA library):
Once you have the calculator example working we can work on implementing the FPGALink USB protocol.
Incidentally, I will hopefully soon have a Parallella board (http://www.parallella.org), which uses the same SoC, so I'll be able to help you with the port.
Chris
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Dylan Ismari
Feb 12, 2014, 1:18:40 PM2/12/14
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I found the Xilinx supplied USB Mass storage application example last week. I have it fully functional with the Host Linux machine being able to format/mount the device using ~256MB of the RAM on the board. Before, reaching out on this forum to you, I was trying to get the ARM core to play nice with this massive data structure and possibly write to it data from the fabric, to no avail ( I am not sure if this is a good way to execute this behaviour).
I have gone through the beyond logic tutorial and found that the Bulk data transfer is the way to go for data transfer. From my understanding, the USB OTG has DMA the ARM core memory space and the USB has 0 access to the fabric ( thus why I have to use the ARM core ). I don't believe implementing FIFO's would be necessary, I would just like the behaviour.
That behaviour being:
The ARM takes data outputted by the fabric HDL and enqueues to the host machine. The host machine really doesn't need to send data to the processor just receive ( I believe this simplifies the behaviour also).
The "calculator" maybe where I am heading. It looks like you are able to do hex dumps from the memory of the FPGA at Hi-speed which has a ton of potential.
The Parallella board looks like fun, the idea of this SOC is amazing. I am just struggling to get a foot-hold with different standards that I just seem to be missing something about.
Thank you very much for the references
-Dylan
I have gone through the beyond logic tutorial and found that the Bulk data transfer is the way to go for data transfer. From my understanding, the USB OTG has DMA the ARM core memory space and the USB has 0 access to the fabric ( thus why I have to use the ARM core ). I don't believe implementing FIFO's would be necessary, I would just like the behaviour.
That behaviour being:
The ARM takes data outputted by the fabric HDL and enqueues to the host machine. The host machine really doesn't need to send data to the processor just receive ( I believe this simplifies the behaviour also).
The "calculator" maybe where I am heading. It looks like you are able to do hex dumps from the memory of the FPGA at Hi-speed which has a ton of potential.
The Parallella board looks like fun, the idea of this SOC is amazing. I am just struggling to get a foot-hold with different standards that I just seem to be missing something about.
Thank you very much for the references
-Dylan
Peter Stuge
Feb 12, 2014, 1:30:20 PM2/12/14
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Dylan Ismari wrote:
> I found the Xilinx supplied USB Mass storage application example last week.
> I have it fully functional with the Host Linux machine being able to
> format/mount the device using ~256MB of the RAM on the board.
That's a very good starting point. It means you do not need to
> I found the Xilinx supplied USB Mass storage application example last week.
> I have it fully functional with the Host Linux machine being able to
> format/mount the device using ~256MB of the RAM on the board.
develop any of the plumbing yourself. You only need to remove lots of
code from the example and instead add in the new calculator operations,
to arrive at a working calculator implementation.
> Before,
> reaching out on this forum to you, I was trying to get the ARM core to play
> nice with this massive data structure and possibly write to it data from
> the fabric, to no avail ( I am not sure if this is a good way to execute
> this behaviour).
USB is highly structured communication, meaning that different uses
of USB can be, and often are, quite different indeed.
Using the MSC example is a great starting point because it is a
working implementation of what would be a significant development
effort, but you should however absolutely not stay with MSC but
instead change how USB is being used, and implement FPGALink.
> That behaviour being:
> The ARM takes data outputted by the fabric HDL and enqueues to the host
> machine. The host machine really doesn't need to send data to the processor
> just receive ( I believe this simplifies the behaviour also).
nice to implement that for FPGALink, and it would probably not be
very much extra effort.
Also, keep in mind that USB is entirely host driven. The ARM may not
send anything until there is application software running on the host
asking the device to send.
FPGALink does hide that however.
> The "calculator" maybe where I am heading.
//Peter
Chris McClelland
Feb 12, 2014, 2:58:13 PM2/12/14
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> From my understanding, the USB OTG has DMA the ARM core memory space and the
> USB has 0 access to the fabric
>
You may be right. That sucks. It means data exchange between the PL
> USB has 0 access to the fabric
>
and USB must go via RAM. Expect somewhat less than the nominal
~40MiB/s that USB typically achieves over bulk endpoints with decent
cables and an otherwise idle bus.
> The host machine really doesn't need to send data to the processor just receive
>
its ideological descendant in this respect: when the host reads from
the FPGA, it first sends a small packet TO the FPGA in order to
initiate the read, providing the logical channel (0-127) to be read
from, and the number of bytes (1-65536).
Chris
Dylan Ismari
Feb 20, 2014, 1:29:57 PM2/20/14
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Still concerning the Zedboard, I discovered today an FTDI chip (FT232H).
I was wondering if this is a similar chip to the FX2 that is found on the Nexys boards? The documentation feels similar.
I was wondering if this is a similar chip to the FX2 that is found on the Nexys boards? The documentation feels similar.
-Dylan
On Tuesday, February 11, 2014 3:39:54 PM UTC-7, Dylan Ismari wrote:
Peter Stuge
Feb 20, 2014, 2:28:44 PM2/20/14
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Dylan Ismari wrote:
> Still concerning the Zedboard, I discovered today an FTDI chip (FT232H).
>
> I was wondering if this is a similar chip to the FX2 that is found on the
> Nexys boards? The documentation feels similar.
It is nowhere near similar.
> Still concerning the Zedboard, I discovered today an FTDI chip (FT232H).
>
> I was wondering if this is a similar chip to the FX2 that is found on the
> Nexys boards? The documentation feels similar.
It's USB full-speed as opposed to high-speed, and it uses an
incredibly inefficient protocol over USB as opposed to the
performance optimized FPGALink protocol.
//Peter
MOISHE FUCHS
Jan 13, 2015, 2:33:06 AM1/13/15
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Hi,
I am using 1 Endpoint for IN & OUT in BULK mode. The IN & OUT end point on the Zynq side has ram buffer. Now, I want to send & receive data from Zynq. Please let me know where & how to start. I do not need the fpga configuration portion.
I am also using Zedboard. I have modified Mass Storage Device & Assigned Digilients VID & PID. The device is detected as follows
| Connection Status | Device connected |
| Current Configuration | 1 |
| Speed | High (480 Mbit/s) |
| Device Address | 1 |
| Number Of Open Pipes | 4 |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 12h | |
| 1 | bDescriptorType | 1 | 01h | Device |
| 2 | bcdUSB | 2 | 0200h | USB Spec 2.0 |
| 4 | bDeviceClass | 1 | 00h | Class info in Ifc Descriptors |
| 5 | bDeviceSubClass | 1 | 00h | |
| 6 | bDeviceProtocol | 1 | 00h | |
| 7 | bMaxPacketSize0 | 1 | 40h | 64 bytes |
| 8 | idVendor | 2 | 1443h | |
| 10 | idProduct | 2 | 0005h | |
| 12 | bcdDevice | 2 | 0104h | 1.04 |
| 14 | iManufacturer | 1 | 01h | "Adithya" |
| 15 | iProduct | 1 | 02h | "B-Scan" |
| 16 | iSerialNumber | 1 | 03h | "2A49876D9CC1AA4" |
| 17 | bNumConfigurations | 1 | 01h |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 0Ah | |
| 1 | bDescriptorType | 1 | 06h | Device Qualifier |
| 2 | bcdUSB | 2 | 0200h | USB Spec 2.0 |
| 4 | bDeviceClass | 1 | FFh | Vendor-Specific |
| 5 | bDeviceSubClass | 1 | 00h | |
| 6 | bDeviceProtocol | 1 | 00h | |
| 7 | bMaxPacketSize0 | 1 | 10h | Should be 64 bytes for high-speed devices |
| 8 | bNumConfigurations | 1 | 00h | Should be greater than zero |
| 9 | bReserved | 1 | 00h |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 09h | |
| 1 | bDescriptorType | 1 | 02h | Configuration |
| 2 | wTotalLength | 2 | 0033h | |
| 4 | bNumInterfaces | 1 | 02h | |
| 5 | bConfigurationValue | 1 | 01h | |
| 6 | iConfiguration | 1 | 01h | "Xilinx" |
| 7 | bmAttributes | 1 | A0h | Bus Powered, Remote Wakeup |
| 4..0: Reserved | ...00000 | |||
| 5: Remote Wakeup | ..1..... | Yes | ||
| 6: Self Powered | .0...... | No, Bus Powered | ||
| 7: Reserved (set to one) (bus-powered for 1.0) |
1....... | |||
| 8 | bMaxPower | 1 | 40h | 128 mA |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 09h | |
| 1 | bDescriptorType | 1 | 04h | Interface |
| 2 | bInterfaceNumber | 1 | 00h | |
| 3 | bAlternateSetting | 1 | 00h | |
| 4 | bNumEndpoints | 1 | 02h | |
| 5 | bInterfaceClass | 1 | FFh | Vendor-Specific |
| 6 | bInterfaceSubClass | 1 | 00h | |
| 7 | bInterfaceProtocol | 1 | 00h | |
| 8 | iInterface | 1 | 00h |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 07h | |
| 1 | bDescriptorType | 1 | 05h | Endpoint |
| 2 | bEndpointAddress | 1 | 81h | 1 In |
| 3 | bmAttributes | 1 | 02h | Bulk |
| 1..0: Transfer Type | ......10 | Bulk | ||
| 7..2: Reserved | 000000.. | |||
| 4 | wMaxPacketSize | 2 | 0200h | 512 bytes |
| 6 | bInterval | 1 | FFh |
| Offset | Field | Size | Value | Description |
|---|---|---|---|---|
| 0 | bLength | 1 | 07h | |
| 1 | bDescriptorType | 1 | 05h | Endpoint |
| 2 | bEndpointAddress | 1 | 01h | 1 Out |
| 3 | bmAttributes | 1 | 02h | Bulk |
| 1..0: Transfer Type | ......10 | Bulk | ||
| 7..2: Reserved | 000000.. | |||
| 4 | wMaxPacketSize | 2 | 0200h | 512 bytes |
| 6 | bInterval | 1 | FFh |
M
Chris McClelland
Jan 13, 2015, 2:45:39 AM1/13/15
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I can't find any suitable programmable USB microcontroller on the ZedBoard schematic. How have you done the mass-storage thing?
Chris
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MOISHE FUCHS
Jan 13, 2015, 3:18:27 AM1/13/15
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Hi,
It has dual ARM processing system. Yes. I configured zedboard as mass storage device
Chris McClelland
Jan 13, 2015, 3:39:15 AM1/13/15
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OK, well you'll need to get the FPGALink firmware working on your board. There is an ARM port[1] that Frank Buss made for the LPC chips, and that has no maintainer currently, so feel free to step up!
Chris
[1] https://github.com/makestuff/libfpgalink/tree/20140524/firmware/lpc
MOISHE FUCHS
Jan 13, 2015, 4:06:33 AM1/13/15
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Hi,
Thank you. I would like to have the start point on host side.
Chris McClelland
Jan 13, 2015, 4:09:44 AM1/13/15
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Once the firmware is ported, you'll be able to use the FPGALink host-side library without modification.
--
MOISHE FUCHS
Jan 13, 2015, 4:42:08 AM1/13/15
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where do I find host side library?
On Wednesday, February 12, 2014 at 4:09:54 AM UTC+5:30, Dylan Ismari wrote:
Chris McClelland
Jan 13, 2015, 4:59:35 AM1/13/15
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