Strange behaviour of the comm_fpga_fx2.vhd logic

[berndl]

Hi Chris,
I'm still on an old VHDL level of your FPGALink (Atlys board, I think I grabbed it E2012...M2013), so if you fixed something in this area just ignore...

I've built a simple test-design for the Atlys, where I only infered a RAM 128 entries of 32bits each. When I simulate this design, I get a strange behaviour. I've initialized my RAM with all zeros. In the Testbench, when I just want to verify that these entries are all zero after "power-on", I'm getting a different value. If I just issue one single write to the RAM (arbitrary address) and read the content of the entire RAM back, then everything works fine.

So, for me it looks like the (ok, old) comm_fpga_fx2.vhd is working correct only after issueing a write command. After the single write everything works as expected, and my designs with FPGALink usually will first set up the logic with write commands before anything is read back, so it isn't a big issue for me.

Is this a known issue? If not, I can provide you my design (simulator is GHDL under Linux). I haven't checked the behaviour of the real HW, that's just a simulation output...

Kind regards,
- Bernd

[Chris McClelland]

Please try with the latest comm-fpga VHDL, and let me know if you still get weird results:

https://github.com/makestuff/comm-fpga/blob/20161106/fx2/vhdl/comm_fpga_fx2.vhdl

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[berndl]

Hi Chris,

after some weeks I found the time to dig into the problem: It's not with 'comm_fpga_fx2'!
The issue is in my wrapper-code around comm_fpga_fx2, basically just a wrong init of a counter (which was corrected with a first write command to the FPGA). Wow, undiscovered since >3 years...