Automatic Layout in Electric VLSI

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2020 11049

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Jan 23, 2022, 10:48:04 AM1/23/22
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Hello,

Can we generate automatic layout by any means in Electric VLSI. Like by using Verilog code to generate layout or any similar thing possible in Electric VLSI.

Gavin

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Jan 23, 2022, 11:23:38 AM1/23/22
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Electric 9.07 was released in 2016 [1].  It looks like that is still the current version on the Electric website [2].

So there probably hasn't been any improvements to Electric for automatic layout, unless such changes have been made in the development source code [3].

The 2017 post at [4] should help with your question.

If you would like to contribute to programming better automatic layout for Electric, the development team may still be looking for a developer.  Refer to post [5].


Kind Regards,
Gavin
Electric VLSI user

Steven Rubin

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Jan 23, 2022, 11:26:53 AM1/23/22
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Electric has placement and routing tools as well as a rudimentary "Silicon Compiler". You can read both VHDL and Verilog but they must be structural, not behavioral (which limits things). Then the automated tools can be run. It's not production-quality, but it works.

   -Steven Rubin

On 1/23/2022 12:03 AM, '2020 11049' via Electric VLSI Editor wrote:
Hello,

Can we generate automatic layout by any means in Electric VLSI. Like by using Verilog code to generate layout or any similar thing possible in Electric VLSI.
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Ashwin Balagopal S ee17d200

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Jan 25, 2022, 11:36:43 PM1/25/22
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Oh that's interesting. I tried it out and it worked pretty well.

What needs to happen to be able to get it to synthesise behavioural netlists?

Ashwin

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Steven Rubin

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Jan 26, 2022, 12:08:25 AM1/26/22
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To be able to handle behavioral Verilog, the compiler (in Electric) needs to be upgraded so it can do the conversion from behavior to structure.

   -Steven Rubin

Joselito Morallo

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Jan 26, 2022, 12:43:44 AM1/26/22
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Hi ElectricVLSI!

I got some info of the Behavioral Representation from an old VLSI book written by NIEL H.E. Weste/Kamran Eshragran that BR representation describes how a particular design should respond to a given set of inputs. Behavior may be specified by Boolean equations, tables of input and output values, or algorithms written in standard high level computer languages or special Hardware Description Languages (HDLs). The Latter include VHDL, Verilog and ELLA.
When Electric was Developed did the Engineers documented the Implementation of the Silicon Compiler in Java? If we need to upgrade the electric tool to convert BD to SD we might need algorithms of all digital circuits like for example adder, multiplier, etc... I guess it will be in Java.

Just my opinion.

BR, Joselito



 

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Gavin

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Jan 26, 2022, 3:41:35 AM1/26/22
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If you go to [1], then click on "view".  The source code header of SilComp.java has on line 6:

* Silicon compiler tool (QUISC): control

The source code has comments in it suggesting that the implementation may be self-documented in the source code itself.  I don't recall ever seeing any other developer documentation for Electric, but if there was it may have been something only the internal development team at Oracle had access to.  Dr. Rubin could probably answer if he was able to take after retirement and could provide to us such documentation, if it existed.

There are Verilog source code files such as VerilogParser.java in the directory at [2].  I remember reading in [3] that a user's experience with the Electric parser was that it lacked handling for standard Verilog.  The software developers have the following comment in VerilogParser.java line 36:

/** * A brain-dead, extremely limited verilog parser. In fact, it really
* doesn't do anything except return a module name with it's port defintions.
*
* <P>Again, this is not meant to be a fully featured parser. It's error handling
* is also not very useful. It is only meant to extract module names and their ports. */

It would most likely be a nice addition if a user could contribute a modification to the source code to upgrade to the Electric Verilog for example to use the IEEE Standard for SystemVerilog [4].


Kind Regards,
Gavin
Electric VLSI user

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