Physical Design from Verilog File to synthesis - floorplanning - placement

[mqamar.ms...@seecs.edu.pk]

Hi, 

i am trying to implement a task that follows 

Synthesis --> Floorplanning --> placement --> Routing 

i am exploring many options 
 
i need urgent guide how to load verilog file and synthesize it 

will higher abstraction level of verilog file code work for it?  or we have to provide a verilog code working at gate level ? 

how to synthesize it? and go to floorplan stage. i am getting a lot of errors while loading a verilog file. 

[Gavin Abo]

In the pdf document titled "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System" at:

https://digital.library.unt.edu/ark:/67531/metadc849770/

it says:

"Electric has two issues with Verilog; Electric has a weak and old parser which can't handle standard Verilog code. The second problem with Electric is that it can't handle behavioral Verilog. Therefore, it cannot understand some of the Verilog code."

Indeed, comments in the Electric source code [ https://github.com/imr/Electric-VLSI/blob/master/electric/electric-core/src/main/java/com/sun/electric/tool/simulation/test/VerilogParser.java ] seem to confirm that as it has:

"... extremely limited verilog parser.  In fact, it really doesn't do anything except return a module name with it's port definitions. Again, this is not meant to be a fully featured parser.  It's error handling is also not very useful.  It is only meant to extract module names and their ports."

Therefore, it might be better to write your own Electric Verilog code rather than try to import one.  For example, the attached file based on the Old Way (QUISC) might help a little.

Although, there is a New Way (Modern) approach that I'm not familiar with that is also described in the Electric manual:

http://www.staticfreesoft.com/jmanual/mchap09-12.html