How to start with DE0-Nano-SoC board?

[euerka]

Dear all,

Recently I read  http://blog.machinekit.io/2016/04/altera-soc-running-machinekit-with.html and i bought one DE0-Nano-Soc board.

From this post I follow this (https://github.com/cdsteinkuehler/mksocfpga/blob/master/HW/README.BuildSystem.txt ) build system guide. As I understand as followings, please correct me if there is any mistakes:
1.On host machine, set up Quartus according above guide
2. clone https://github.com/machinekit/mksocfpga and compile firmware
3. prepare SD image as normal
4. Copy firmware to /boot
5. insert SD card to SoC board and boot

Please give me more hints to start with this SoC board,
Thanks!
-chengxi

[Charles Steinkuehler]

On 8/24/2016 9:32 AM, euerka wrote:
> Dear all,
>
> Recently I
> read_http://blog.machinekit.io/2016/04/altera-soc-running-machinekit-with.html_

> <http://blog.machinekit.io/2016/04/altera-soc-running-machinekit-with.html> and
> i bought one DE0-Nano-Soc board.
>
> From this post I follow

> this_(https://github.com/cdsteinkuehler/mksocfpga/blob/master/HW/README.BuildSystem.txt_
> <https://github.com/cdsteinkuehler/mksocfpga/blob/master/HW/README.BuildSystem.txt>__)

> build system guide. As I understand as followings, please correct me if there is
> any mistakes:
> 1.On host machine, set up Quartus according above guide
> 2. clone https://github.com/machinekit/mksocfpga and compile firmware
> 3. prepare SD image as normal
> 4. Copy firmware to /boot
> 5. insert SD card to SoC board and boot
>
> Please give me more hints to start with this SoC board,

Unless you really need to build from source, you should use one of the
uSD image (and look at the README file) from:

http://deb.mah.priv.at/uploads/de0-nano/

The process of fully automating builds of the uSD images from source
is nearly complete, but at the moment things are moving a bit quickly
(but everything still generally works).

Even if you need to build from source, I suggest you start with the
image to get familiar with the system. Then you can replicate as much
(or little) of the build process as needed for your application. The
details for building the various bits and pieces are contained in the
Jenkins build jobs.

--
Charles Steinkuehler
cha...@steinkuehler.net

[Michael Haberler]

Hi Chengxi

there is nothing released yet but as Charles said - we're getting close

meanwhile please read through the last thread 'How to cross compile machinekit to run on the zedboard?' to catch up, and follow the issues suggested therein, plus in particular https://gist.github.com/mhaberler/89a813dc70688e35d8848e8e467a1337

- Michael

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[euerka]

Hi Charles,

Just for update. I have run machinekit on DE0-Nano-SoC successful.
It is the time to enter FPGA things, if I am not wrong, i have to build <https://github.com/machinekit/mksocfpga> as FPGA firmware, then use hm2_soc_ol  as driver to let machinekit talk with FPGA.

Now I am running 32 bit ubuntu, it seems i can not install docker or recently Quartus-15.1.2
Does old version work?

Thanks!
-chengxi

[Charles Steinkuehler]

On 10/31/2016 7:43 AM, euerka wrote:
> Hi Charles,
>
> Just for update. I have run machinekit on DE0-Nano-SoC successful.
> It is the time to enter FPGA things, if I am not wrong, i have to build

> <_/https://github.com/machinekit/mksocfpga/_> as FPGA firmware, then use
> *hm2_soc_ol *as driver to let machinekit talk with FPGA.

>
> Now I am running 32 bit ubuntu, it seems i can not install docker or recently
> Quartus-15.1.2

> <https://github.com/cdsteinkuehler/QuartusBuildVMs/tree/master/Jessie-Quartus-15.1.2>
> Does old version work?

There is no need to build anything locally unless you are doing FPGA
development. Just install the package with the bitfiles:

sudo apt-get install socfpga-rbf

--
Charles Steinkuehler
cha...@steinkuehler.net

[euerka]

Yeah, I would like to do FPGA development in future, since I have no plan to use Mesa board.
Due to I have Zero knowledge about it, I think this is a good example to start to learn about it.
Anyhow as you suggested before, I will download and try to run it first.

Thanks!
-chengxi

[Bas de Bruijn]

> On 31 Oct 2016, at 14:33, euerka <crazyin...@gmail.com> wrote:
>
> Yeah, I would like to do FPGA development in future, since I have no plan to use Mesa board.

All the functions of the hostmot2 firmware are available on the pins of the board. It's not mandatory to have mesa hardware connected. And to my knowledge it's trivial to make your own pin layout. So if you want stepgens, encoders and whatnot, then it's basically a matter of defining which pins need which function

[euerka]

Hi,

I was just a few days away. Thanks for your reply.
I just Just install the package with the bitfiles as Charles advices:
sudo apt-get install socfpga-rbf

and selected /configs/hm2-soc-stepper/5i25-socfpga.ini, but it failed. linuxcnc.log shows as (http://pastebin.com/z1L4X4vY).

It seems can not found device_tree overlay files

Nov  6 12:01:18 arm msgd:0: hal_lib:5132:rt hm2_soc_ol: mkdir(/sys/kernel/config/device-tree/overlays/hm2-socfpg0) failed: No such file or directory
Nov  6 12:01:18 arm msgd:0: hal_lib:5132:rt hm2/foo: failed to program fpga, aborting hm2_register
Nov  6 12:01:18 arm msgd:0: hal_lib:5132:rt foo: hm2_soc_ol_board fails HM2 registration
Nov  6 12:01:18 arm msgd:0: hal_lib:5132:rt hm2_soc_ol: error registering UIO driver
Nov  6 12:01:18 arm msgd:0: rtapi_app:5132:user hal_call_usrfunct(newinst,config="firmware=socfpga/dtbo/DE0_Nano_SoC_DB25.7I76_7I85S_GPIO_GPIO.dtbo num_stepgens=4 num_encoders=1 num_mencoders=4") failed: -1 - Operation not permitted

Then it start to remove all components. May I know after i installed socfpga-rbf, any hardware configuration should be done in advance?

Thanks for any hints.

-chengxi
 

[Charles Steinkuehler]

On 11/6/2016 6:51 AM, euerka wrote:
> Hi,
>
> I was just a few days away. Thanks for your reply.
> I just Just install the package with the bitfiles as Charles advices:
> sudo apt-get install socfpga-rbf
>
> and selected /configs/hm2-soc-stepper/5i25-socfpga.ini, but it failed.

I'm not sure what's going wrong, I haven't tested on physical hardware
since the FPGA programming got migrated to using device-tree overlays.
I'll dig out my DE0 board and see if I can reproduce the issue.

In the mean time, you might review the github issue thread where
Michael was implementing the hm2_soc_ol driver and verify you've got
the proper kernel (IIRC some of the FPGA programming stuff needed to
be patched into the kernel tree as it hasn't all been merged upstream
yet).

--
Charles Steinkuehler
cha...@steinkuehler.net

[euerka]

Hi Charles,

Thanks, I will review the github issue thread.

-chengxi .

[schoo...@btinternet.com]

I have been playing with this today now that I have an interface board.

Previously with the debian-8.4 image ( I think as this is the one I had
saved ), I could see all the hm2 pins

Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2: loading Mesa
HostMot2 driver version 0.15
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2_soc_ol: loading
Mesa AnyIO HostMot2 socfpga overlay driver version 0.9
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0: IDRom:
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
IDRom Type: 0x00000003
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Offset to Modules: 0x00000040
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Offset to Pin Description: 0x000001C0
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Board Name: TERADE0N
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
FPGA Size: 9
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
FPGA Pins: 144
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Port Width: 17
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0: IO
Ports: 4
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0: IO
Width: 68
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Clock Low: 50000000 Hz (50000 KHz, 50 MHz)
Jul 26 10:25:10 mksocfpga msgd:0: hal_lib:5742:rt hm2/hm2_de0n.0:
Clock High: 200000000 Hz (200000 KHz, 200 MHz)
etc etc

Now , both with an upgraded 8.4 image and a new 8.5 image, the
hm2_soc_ol module errors thus

Nov 12 15:05:36 mksocfpga msgd:0: startup pid=2818 flavor=rt-preempt
rtlevel=1 usrlevel=1 halsize=524288 shm=Posix gcc=4.9.2 version=unknown
Nov 12 15:05:36 mksocfpga msgd:0: ØMQ=4.0.5 czmq=3.0.2 protobuf=2.6.1
libwebsockets=<no version symbol>
Nov 12 15:05:36 mksocfpga msgd:0: configured: sha=ba632dd
Nov 12 15:05:36 mksocfpga msgd:0: built: Nov 12 2016 12:30:29
sha=ba632dd
Nov 12 15:05:36 mksocfpga msgd:0: register_stuff: actual hostname as
announced by avahi='mksocfpga.local'
Nov 12 15:05:36 mksocfpga msgd:0: zeroconf: registering: 'Log service on
mksocfpga.local pid 2818'
Nov 12 15:05:36 mksocfpga msgd:0: rtapi_app:2823:user accepting commands
at ipc:///tmp/0.rtapi.a42c8c6b-4025-4f83-ba28-dad21114744a
Nov 12 15:05:36 mksocfpga msgd:0: hal_lib:2823:rt hm2: loading Mesa
HostMot2 driver version 0.15
Nov 12 15:05:37 mksocfpga msgd:0: hal_lib:2823:rt hm2_soc_ol: loading
Mesa AnyIO HostMot2 socfpga overlay driver version 0.9
Nov 12 15:05:37 mksocfpga msgd:0: zeroconf: registered 'Log service on
mksocfpga.local pid 2818' _machinekit._tcp 0 TXT
"uuid=a42c8c6b-4025-4f83-ba28-dad21114744a"
"instance=7759df84-a8e9-11e6-9629-bad04a9c4ece"
Nov 12 15:05:39 mksocfpga rtapi:0:

hal_call_usrfunct(newinst,config="firmware=socfpga/dtbo/DE0_Nano_SoC_DB25.7I76_7I85S_GPIO_GPIO.dtbo
num_stepgens=4 num_encoders=1 num_mencoders=4") failed: -1 - Operation
not permitted

Nov 12 15:05:39 mksocfpga msgd:0: hal_lib:2823:rt hm2_soc_ol: failed to
map hm2-socfpg0 to /dev/uioX
Nov 12 15:05:39 mksocfpga msgd:0: hal_lib:2823:rt hm2_soc_ol:
soc_mmap_fail hm2-socfpg0
Nov 12 15:05:39 mksocfpga msgd:0: hal_lib:2823:rt hm2/foo: failed to
program fpga, aborting hm2_register
Nov 12 15:05:39 mksocfpga msgd:0: hal_lib:2823:rt foo: hm2_soc_ol_board
fails HM2 registration
Nov 12 15:05:39 mksocfpga msgd:0: hal_lib:2823:rt hm2_soc_ol: error
registering UIO driver
Nov 12 15:05:39 mksocfpga msgd:0: rtapi_app:2823:user

hal_call_usrfunct(newinst,config="firmware=socfpga/dtbo/DE0_Nano_SoC_DB25.7I76_7I85S_GPIO_GPIO.dtbo
num_stepgens=4 num_encoders=1 num_mencoders=4") failed: -1

Nov 12 15:05:40 mksocfpga msgd:0: hal_lib:2823:rt hm2: ignoring request
to unregister foo: not found
Nov 12 15:05:40 mksocfpga msgd:0: hal_lib:2823:rt hm2: unloading

This happens irrespective of whether there is a 7i76 attached and is so
early in the process that it is something fairly fundamental
eg
`hm2_soc_ol: failed to map hm2-socfpg0 to /dev/uioX`

I am currently in the process of making a debian-8.4 image based card
and trying that, in the meanwhile any ideas???

BTW the debian-8.5 image does not seem to include `xauth`, so that needs
to be added before you can ssh into it and get X forwarding working.

[schoo...@btinternet.com]

For whatever reason, the debian-8.5 image does not work

Just wrote the 8.4 image and did NOT upgrade anything and although not
tested yet, the pins are created

[schoo...@btinternet.com]

I have temporarily hosted it at

http://www.mgware.co/uk/temp/debian-8.4-machinekit-de0-armhf-2016-07-20-4gb.bmap
and
http://www.mgware.co/uk/temp/debian-8.4-machinekit-de0-armhf-2016-07-20-4gb.img.xz

Create the card image with
bmaptool copy debian-8.4-machinekit-de0-armhf-2016-07-20-4gb.img  /dev/sdX
from the extracted image

Set the MAC code for the NIC on first boot as before, but when booted into the rootfs, update apt but do not run
apt-get upgrade, or you will get later files and kernel and this is what does not work for me

regards

On 13/11/16 11:36, Chen Cheng Xi wrote:

Dear schooner,

Would you mind share with me the debian-8.4 image link?

I am struggle with it now.

Thanks!

-chengxi

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[schoo...@btinternet.com]

URLs got corrupted somehow

Should of course be

http://www.mgware.co.uk/temp/debian-8.4-machinekit-de0-armhf-2016-07-20-4gb.bmap
and
http://www.mgware.co.uk/temp/debian-8.4-machinekit-de0-armhf-2016-07-20-4gb.img.xz

ie dot not forward slash after co

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[schoo...@btinternet.com]

Update to below

This morning I have been able to get a turret knee mill in my workshop, which already has a 7i76
board in the controller head, working with the DE0-Nano-Soc

This after the semi-obligatory 'brain-fade' where I forgot how I had powered the 5v source to the 7i76
and could not work out why the 7i76 was 'missing'.
The answer is that the DE0-Nano does NOT supply a 5v feed as the 5i25 will do, so you must wire
one in and change the W2 jumper accordingly - thanks for the prompt Bas!

I used the debian-8.4 image as below, NOT upgraded.
As previously, there is some as yet undetermined problem with the instantiable driver, or the related
changes in the later image. 
The earlier driver and image work fine though.

The configuration is identical to my original 5i25-7i76 one, except for the [HOSTMOT2] section of the ini

[HOSTMOT2]
DRIVER=hm2_soc_ol
BOARD=de0n
CONFIG="firmware=socfpga/dtbo/DE0_Nano_SoC_DB25.7I76_7I76_7I76_7I76.dtbo num_encoders=2 num_stepgens=4"

The .hal file begins with

loadrt trivkins
loadrt tp
loadrt [EMCMOT]EMCMOT servo_period_nsec=[EMCMOT]SERVO_PERIOD num_joints=[TRAJ]AXES  tp=tp kins=trivkins
loadrt hostmot2 debug_idrom=1 debug_modules=1
loadrt [HOSTMOT2](DRIVER) config=[HOSTMOT2](CONFIG)

NB. if you copy & paste from the sample config, note that tp=tp kins=trivkins is commented out in that config

The eagle eyed amongst you may have spotted that I specified encoders=2 in the config line

Each header on the 5i25 and thus the Nano, only has 4 stepgens and 1 encoder, what this does is effectively enable the second DB25 header output socket on Charles's
interface board (equivalent to the header P2 on the 5i25) and the encoder.01 can be accessed from that.

I use the second encoder solely for a hardware pendant MPG on this mill, all the IO for the switches etc on that pendant go onto the 7i76 and are dealt with on the primary header.

My aim for the DE0-Nano, is to replace the parport based controller setup on my slant-bed lathe, with this board and interface running headless and
accessed via the existing computer with the lathe

Congratulations and thanks to Charles Steinkuehler, Michael Haberler, Michael Brown and Devin Hughes for their parts in getting this to fruition.

It is a major achievement

[Charles Steinkuehler]

On 11/14/2016 8:38 AM, schoo...@btinternet.com wrote:
> Update to below
>
> This morning I have been able to get a turret knee mill in my workshop, which
> already has a 7i76
> board in the controller head, working with the DE0-Nano-Soc

Great progress!

> This after the semi-obligatory 'brain-fade' where I forgot how I had powered the
> 5v source to the 7i76
> and could not work out why the 7i76 was 'missing'.
> The answer is that the DE0-Nano does NOT supply a 5v feed as the 5i25 will do,
> so you must wire
> one in and change the W2 jumper accordingly - thanks for the prompt Bas!

The W1 and W2 jumpers on my interface should allow you to provide 5V
to the 7i76, just like the 5i25.

With either the 5i25 or my board, you have to have field power to the
7i76 smart-serial logic when you load the hm2_soc_ol for any of the
7i76 GPIOs to be detected. Is that what was going wrong?

--
Charles Steinkuehler
cha...@steinkuehler.net

[schoo...@btinternet.com]

On 14/11/16 14:46, Charles Steinkuehler wrote:
> This after the semi-obligatory 'brain-fade' where I forgot how I had powered the
> 5v source to the 7i76
> and could not work out why the 7i76 was 'missing'.
> The answer is that the DE0-Nano does NOT supply a 5v feed as the 5i25 will do,
> so you must wire
> one in and change the W2 jumper accordingly - thanks for the prompt Bas!
> The W1 and W2 jumpers on my interface should allow you to provide 5V
> to the 7i76, just like the 5i25.

Ah, that seems obvious now you say it, but never seen a manual for it ;-)

I have some reservations as to whether the PSU with the DE0-Nano would
be up to supplying the 7i76 as well, so separate power might be best

>
> With either the 5i25 or my board, you have to have field power to the
> 7i76 smart-serial logic when you load the hm2_soc_ol for any of the
> 7i76 GPIOs to be detected. Is that what was going wrong?
>

Exactly, I thought I had wired the 7i76 to a 5v supply in the controller
head, but had in fact
used that supply later for the pendant MPG and changed it to draw from
the 5i25, a fact I had forgotten.

[euerka]

Recently I got an email <http://mail.terasic.com.tw/epaper/2017/Products/en/de0-nano-eof/>

DE0-Nano-SoC was end of life.

By the way, now my board is work with Schooner's img.
As he mentioned in previous post, 7i76 board was used as interface board?

Does it work only with GPIO in board? If so, may I know the hardware configuration the same as Beaglebone P8,P9?

Thanks!

[Bas de Bruijn]

> On 16 Mar 2017, at 15:07, euerka <crazyin...@gmail.com> wrote:
>
> Does it work only with GPIO in board? If so, may I know the hardware configuration the same as Beaglebone P8,P9?

What do you mean?

The 7i76 and other boards can be used with Charles' adapter board for example. Which provides the connection as it were an 5i25 PCI card.

There's no relation with Beaglebone pinout.

[schoo...@btinternet.com]

On 16/03/17 14:07, euerka wrote:

Recently I got an email <http://mail.terasic.com.tw/epaper/2017/Products/en/de0-nano-eof/>

DE0-Nano-SoC was end of life.

By the way, now my board is work with Schooner's img.
As he mentioned in previous post, 7i76 board was used as interface board?

Does it work only with GPIO in board? If so, may I know the hardware configuration the same as Beaglebone P8,P9?

This is the GPIO pinout
https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd#L376-L450

I have one machine running with stepgens and an encoder off the P2 header and just using GPIO off the P3 header on one of Charles's
interface boards for all the limits, home, estop etc

Attached is the GPIO pinout to physical DB25 pins

Thanks!

[Chen Cheng Xi]

Thanks schooner, this is exactly what I want to know.

Since I used beaglebone PRU GPIO to connect A4498 stepper motor driver before, If I am not wrong, I just use GPIO 0 and 1 to connect with A4498.

I will try it soon.

-chengxi

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[Chen Cheng Xi]

Hi,

I am trying to looking for pins such as Dir/Step, unfortunately I can't find them at all.

[schoo...@btinternet.com]

The output pins of the DB25 board are the same as the Mesa 5i25

There are no step and dir software pins because the steps are produced in hardware, you just need to connect your stepper

driver to the appropriate DB25 pins and use the software params to set the timing etc.

Same applies to encoder, A, B and Index are physical pins

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[Charles Steinkuehler]

The FPGA pin functions depend on which FPGA bitfile you load when
loading the hm2 driver. The driver will spit out a list of all the
functions it finds, but you can also refer to the configuration files
for each FPGA "flavor" in the source. The VHDL file defining the pins
has comments with the internal MESA I/O pin number, the Physical
DE0-Nano-SoC I/O connector pin, and the DB-25 pin (when used with my
DB25 daughter card). Here's the configuration for one 7i76, one
7i85s, and two plain GPIO connectors. I've highlighted the 7i76 pins:

https://github.com/machinekit/mksocfpga/blob/master/HW/hm2/config/DE0_Nano_SoC_DB25/PIN_7I76_7I85S_GPIO_GPIO.vhd#L111-L129

On 3/18/2017 2:32 AM, schoo...@btinternet.com wrote:
> The output pins of the DB25 board are the same as the Mesa 5i25
>
> There are no step and dir software pins because the steps are produced in
> hardware, you just need to connect your stepper
>
> driver to the appropriate DB25 pins and use the software params to set the
> timing etc.
>
> Same applies to encoder, A, B and Index are physical pins
>
> On 18/03/2017 03:10, Chen Cheng Xi wrote:
>> Hi,
>>
>> I am trying to looking for pins such as Dir/Step, unfortunately I can't find
>> them at all.

>> Inline image 1Inline image 2

>>
>> On Fri, Mar 17, 2017 at 10:19 PM, Chen Cheng Xi <crazyin...@gmail.com
>> <mailto:crazyin...@gmail.com>> wrote:
>>
>>
>> Thanks schooner, this is exactly what I want to know.
>> Since I used beaglebone PRU GPIO to connect A4498 stepper motor driver
>> before, If I am not wrong, I just use GPIO 0 and 1 to connect with A4498.
>>
>> I will try it soon.
>> -chengxi
>>
>> On Fri, Mar 17, 2017 at 12:06 AM, schoo...@btinternet.com

>> <mailto:schoo...@btinternet.com> <schoo...@btinternet.com

>> <mailto:schoo...@btinternet.com>> wrote:
>>
>>
>> On 16/03/17 14:07, euerka wrote:
>>> Recently I got an email

>>> /_<http://mail.terasic.com.tw/epaper/2017/Products/en/de0-nano-eof/
>>> <http://mail.terasic.com.tw/epaper/2017/Products/en/de0-nano-eof/>_/>

>>>
>>> DE0-Nano-SoC was end of life.
>>>
>>> By the way, now my board is work with Schooner's img.
>>> As he mentioned in previous post, 7i76 board was used as interface board?
>>>
>>> Does it work only with GPIO in board? If so, may I know the hardware
>>> configuration the same as Beaglebone P8,P9?
>>
>> This is the GPIO pinout
>> https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd#L376-L450
>> <https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd#L376-L450>
>>
>> I have one machine running with stepgens and an encoder off the P2
>> header and just using GPIO off the P3 header on one of Charles's
>> interface boards for all the limits, home, estop etc
>>
>> Attached is the GPIO pinout to physical DB25 pins
>>>
>>> Thanks!
>>>
>>
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--

Charles Steinkuehler
cha...@steinkuehler.net

[Schooner]

On Thursday, 16 March 2017 14:07:24 UTC, euerka wrote:

Recently I got an email <http://mail.terasic.com.tw/epaper/2017/Products/en/de0-nano-eof/>

DE0-Nano-SoC was end of life.

I have had one of these too

Looking at the replacement the DE10, it seems pretty much the same with one big difference, it has a HDMI output.

They are not in stock currently, so obviously in a transition between the 2 boards, but will be interesting to see what video capabilities it has
and whether it potentially could be a completely standalone controller, without using it headless from another device.

[Michael Brown]

I have 2 DE10-Nano boards.  (Need them for my synthesizer project)

Expect the graphic capabilities to be:

A basic (linux)framebuffer good enough for 2D, however without OpenGL

That is unless you invest in some of the paid OpenGL cores for Cyclone V out there....

BTW the fpga is also upgraded to the largest chip in the series so plenty of space....

Best wishes

Michael B.

[Chen Cheng Xi]

Thanks Charles,

I have read 7i76 pins link and also about your DB25 daughter card( https://blog.oshpark.com/tag/db25/).

If I am not mistake,40 pins in DB25 daughter card P1 will connect to DE0-NANO-SOC JP1 GPIO 0, then split into 2 DB25 P2 and P3.

From the configs file, take one example, GPIO_0 pin 16, 17 (physic 17,18 because on board label from 1), means DIR and STEP which will connect to DB25 pin 1 and pin 14.

I use multi-meter to measure Pin 17 and GND, then run NC program moving X,Y,Z together, unfortunately no votage output from this pin.

-chengxi 

[Charles Steinkuehler]

Refer to the DE0-Nano-SoC schematic (found on the CD-ROM:
http://www.terasic.com/downloads/cd-rom/de0-nano-soc/) and you will
see that the signal GPIO_0 16 is physically on header JP1, pin 19 and
signal GPIO_0 17 is physically on header JP1, pin 20.

In addition to the different starting pin number (0 vs. 1), the JP1
header has some power and ground pins between groups of I/O signals,
which isn't mentioned in the User's Guide.

On 3/18/2017 9:56 PM, Chen Cheng Xi wrote:
> Thanks Charles,
>
> I have read 7i76 pins link and also about your DB25 daughter

> card(_https://blog.oshpark.com/tag/db25/_).

> <https://github.com/machinekit/mksocfpga/blob/master/HW/hm2/config/DE0_Nano_SoC_DB25/PIN_7I76_7I85S_GPIO_GPIO.vhd#L111-L129>

[Chen Cheng Xi]

Thanks again Charles,

Yeah, I got the same measurement value as you mentioned and summarized as below:

JP1 header:

     Pin 15 : Z Dir

     Pin 16 : Z STEP
     Pin 15 : Y Dir
     Pin 16 : Y STEP 

     Pin 15 : X Dir
     Pin 16 : X STEP

I am going to connect it to step driver A4988 soon and see how.

Best regards!

-chengxi

[Charles Steinkuehler]

On 3/18/2017 9:28 AM, Schooner wrote:
>
> They are not in stock currently, so obviously in a transition between the 2
> boards, but will be interesting to see what video capabilities it has
> and whether it potentially could be a completely standalone controller, without
> using it headless from another device.

There is no GPU on these chips, so while they can easily drive an HDMI
display from a framebuffer, there will be little or no 2D or 3D
acceleration unless you build a GPU from FPGA gates.

So video performance will be pretty bad (compared to an ARM SoC with a
Linux supported GPU).

...but it might be good enough with the proper user interface. I'm
still waiting for someone to make a non-3D interface for the
BeagleBone that works well with the lower-resolution wide-screen HDMI
input LCD screens available for cheap on eBay (ie: 7-inch 800x480).

--
Charles Steinkuehler
cha...@steinkuehler.net