uvm_config_db #(uvm_object_wrapper)::set(this,"pci_agt.sqr.main_phase","default_sequence",pci_run_sequence::get_type()) is not working well.

[Michael Li]

Hi EDA Playground,

1. uvm_config_db #(uvm_object_wrapper)::set(this,"pci_agt.sqr.main_phase","default_sequence",pci_run_sequence::get_type());   Simulation only allows 1 transaction to be sent to the driver and then immediately ends.

2. Using start(), the simulation will complete as many transactions as I like.   

task run_phase(uvm_phase phase);

  test_seq = pci_run_sequence::type_id::create("test_seq");

  phase.raise_objection(this, "starting test_seq");

  test_seq.start(pci_agt.sqr);

  phase.drop_objection(this, "finished test_seq");

endtask: run_phase

I think this is a bug.   I want to report it to you.

Best,

Michael

[Victor Lyuboslavsky]

Michael,

Please provide a link to your saved code so that we can investigate.

Since we use ModelSim 10.1d for the UVM simulation, there may be a simulator issue.

Thanks,
Victor

[Victor Lyuboslavsky]

Your code works fine with UVM 1.1d but not with UVM 1.2

In UVM 1.2, you cannot directly access starting_phase, you must use get_starting_phase()
http://eda-playground.readthedocs.org/en/latest/_static/uvm-1.2/files/overviews/relnotes-txt.html#Mantis_4431%28*%29%28+%29

You can see the issue by adding this flag to the compile options: +define+UVM_NO_DEPRECATED

[Michael Li]

Hi Victor,

Thank you.   You are right.    They are flagged after I added  +define+UVM_NO_DEPRECATED.     

I found your example link on internet.   I put set_automatic_phase_objection(1);  in the constructor and it works now for UVM 1.2!!!  Here is my new code.  http://www.edaplayground.com/x/3gU    It works even with a nested sequence.

I have a concern.   I need your help.

1.  After looking through the sequence_base class code, set_automatic_phase_objection seems to raise a new objection for every child sequence in a nested parent sequence.    Is that true?    That will be different from my original code which raises objection only for the parent sequence.   I am concerned if it would slow down the simulation.

  if (get_parent_sequence() == null && starting_phase() != null)    // my original code

     starting_phase.raise_objection(this);

2. So, I try to use set_starting_phase only for the parent sequence with my original code concept.     It does not work.   I am confused with the purpose of set_starting_phase.   There is not an unset function for starting phase.   Could you help me?

task pre_start;

  if (get_parent_sequence() == null && get_starting_phase() != null)

      this.set_starting_phase(null);         // null is not right either.   It should be a phase name.   I can't get a phase name from sequencer.

endtask

task post_start;

  //if (get_parent_sequence() == null && get_starting_phase() != null)

  //    starting_phase.drop_objection(this);       // not even sure what to use here

endtask:  post_start

# UVM_ERROR /playground_lib/uvm-1.2/src/dap/uvm_get_to_lock_dap.svh(67) @ 30: reporter [UVM/GET_TO_LOCK_DAP/SAG] Attempt to set new value on 'pci_run_sequence.starting_phase', but the data access policy forbids setting after a get!

http://www.edaplayground.com/x/ZR

Can you help me again? Thank you.

Michael

--
You received this message because you are subscribed to a topic in the Google Groups "EDA Playground" group.
To unsubscribe from this topic, visit https://groups.google.com/d/topic/eda-playground/GtZTJtU0tkw/unsubscribe.
To unsubscribe from this group and all its topics, send an email to eda-playgroun...@googlegroups.com.

To view this discussion on the web visit https://groups.google.com/d/msgid/eda-playground/43f6d126-a84f-4376-82a7-3e6a0a3a8b9a%40googlegroups.com.

For more options, visit https://groups.google.com/d/optout.

[Michael Li]

Maybe I understand now.

1. set_automatic_phase_objection is to setup the auto mechanism for raising objections and dropping objections for sequences.

2. set_starting_phase is to assign the phase (ie main_phase) to start the sequence.

They are two different functions.   It seems that I would not be able to go back to my old code concept for UVM 1.2.

Michael

[Victor Lyuboslavsky]

1. I haven't played with set_automatic_phase_objection too much. I imagine you should be able to set it only for parent sequence and not set it for child sequence.

2. Setting starting phase is typically done from a higher level uvm component such as agent or environment. Also, UVM 1.2 has phase introspection, so you can traverse the phase graph: https://www.youtube.com/watch?v=WVhNrFL2874&list=SPScWdLzHpkAdYPk_jgxRgOPisTm3-7U6A

[Michael Li]

Thank you again.   Then I will play around with set_automatic_phase_objection.     The video is very helpful to give me some idea on the usage of these get/set_ functions.  .    Thank you for your videos on youtube.

Best,

Michael

[wilso...@gmail.com]

HI Victor,

After migrating to UVM 1.2 I am getting meta character warning. Please let me know the process to avoid this.

UVM_WARNING /remote/vip/apps/UVM/uvm-1.2/uvm-1.2/src/base/uvm_resource.svh(1416) @ 0.00 ps: reporter [UVM/RSRC/NOREGEX] a resource with meta characters in the field name has been created "device0.satasvc_device_vars"

Thanks,

Wilson

[Victor Lyuboslavsky]

Wilson,

UVM 1.2 added some strict checks for instance names and field names to prevent potential issues. It seems like you're hitting one of those issues.

If you have an EDA Playground link to the code, I can take a look.

Regards,
Victor