Infer BRAM on Xilinx FPGAs using Chisel Queue

[Lorenzo Di Tucci]

Hi all, 

I am trying to create a Fifo to interface my core with the DDR. So far I have been successful using the Queue Chisel Module, however, I would like to have them implemented as BRAM on the FPGA, as the way is implemented in Chisel uses too many LUTS.

Do you have any suggestion on how this can be made?

Thanks

Lorenzo

[Yaman Umuroglu]

Hi Lorenzo,

If you don't mind Chisel2 code, here is one suggestion as to how this could be done:

https://github.com/maltanar/fpga-tidbits/blob/master/src/main/scala/fpgatidbits/ocm/FPGAQueue.scala

In turn, this uses the DualPortBRAM component located in the same directory, which is a BlackBox (with a simple behavioural model for emulation). The actual Verilog that correctly infers dual-port BRAMs for these in synthesis is here:

https://github.com/maltanar/fpga-tidbits/blob/master/src/main/verilog/DualPortBRAM.v

I realize this isn't the most elegant way but this worked for me. For an explanation why it was done this way, here's a post from 2015:

https://groups.google.com/forum/?utm_source=digest&utm_medium=email/#!searchin/chisel-users/bram%7Csort:date/chisel-users/RbhcbsHE2eE/lW4WHMT1CAAJ

Best regards,

Yaman

[Lorenzo Di Tucci]

Hi Yaman,

thank you very much for the suggestion. I took a look at your code and it is great! However, I had some issues in integrating it with all the rest of the code that was written in Chisel3 (I am not so skilled with chisel).

I ended up using your methodology and I have created a black box, and then I have manually inserted BRAM FIFO Macro available within Vivado. It instantiates BRAM correcly during synthesis and now I am generating  the bitstream for checking its functionality.

It is a pity that Chisel does not provides such functionality!

Thanks

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- Lorenzo