Problems with Chisel 3.0 and Verilator

[Øyvind Harboe]

I'm having problems with Chisel 3.0 and Verilator 3_866 (I tried newer and older versions of Verilator without luck).

I don't understand what's going on, but the problem seems to be somewhat similar to https://github.com/jamesbowman/swapforth/issues/43

The below below has to be precious little to go on, but I was hoping that it would ring a bell and that the group could offer some pointers.

Here's the log output(heavily edited to shorten output):

verilator --cc system_loaddata.v --assert -Wno-fatal -Wno-WIDTH -Wno-STMTDLY --trace -O1 --top-module system_loaddata +define+TOP_TYPE=Vsystem_loaddata +define+PRINTF_COND=!system_loaddata.reset +define+STOP_COND=!system_loaddata.reset -CFLAGS -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=Vsystem_loaddata -include Vsystem_loaddata.h -Mdir test_run_dir --exe system_loaddata-harness.cpp

[various warnings messages deleted, but the below may be relevant]

%Warning-UNOPTFLAT: test_run_dir/system_loaddata.v:201415: Signal unoptimizable: Feedback to clock or circular logic: system_loaddata.Proc.storer_31_1.u32Address

%Warning-UNOPTFLAT:      Example path: test_run_dir/system_loaddata.v:201415:  system_loaddata.Proc.storer_31_1.u32Address

%Warning-UNOPTFLAT:      Example path: test_run_dir/system_loaddata.v:201603:  ASSIGNW

%Warning-UNOPTFLAT:      Example path: test_run_dir/system_loaddata.v:201425:  system_loaddata.Proc.storer_31_1._T_54

%Warning-UNOPTFLAT:      Example path: test_run_dir/system_loaddata.v:201415:  system_loaddata.Proc.storer_31_1.u32Address

g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=1 -DVM_COVERAGE=0 -Wno-char-subscripts -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=Vsystem_loaddata -include Vsystem_loaddata.h   -c -o system_loaddata-harness.o system_loaddata-harness.cpp

[other g++ deleted]

system_loaddata-harness.cpp: In member function ‘void system_loaddata_api_t::init_sim_data()’:

[lots of similar errors as to the below deleted]

system_loaddata-harness.cpp:718:62: error: ‘class Vsystem_loaddata’ has no member named ‘system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram’

         sim_data.signals.push_back(new VerilatorSData(&(dut->system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram[i])));

 

[Stefan Wallentowitz]

Hi Øyvind,

On 22.02.2017 15:48, Øyvind Harboe wrote:

>
> system_loaddata-harness.cpp:718:62: error: ‘class Vsystem_loaddata’ has
> no member named
> ‘system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram’
> sim_data.signals.push_back(new
> VerilatorSData(&(dut->system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram[i])));

Do you have a repo from that I could reproduce it?

Cheers,
Stefan

[Jack Koenig]

While I do not think it is the cause of this issue, chisel3 and firrtl require at least Verilator 3.886 or newer (https://github.com/ucb-bar/firrtl#prerequisites).

The errors seem to be indicating a piece of circular logic in your code. Is u32Address a Wire that gets connected to itself or something?

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[Øyvind Harboe]

I have tried 3.886 as well as 3.900 w same results.

w.r.t. circular logic u32Address, could that be a separate problem?

I am looking into the possibility of stripping down my project and share the code. (not a technical problem).

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[Jack Koenig]

I mention the version number because once this problem is resolved you will probably run into issues with that.

Combinational loops are not allowed in Chisel nor Verilator. So if Verilator is reporting circular logic, that is probably the issue.

To view this discussion on the web visit https://groups.google.com/d/msgid/chisel-users/CACELUGehdECL3FH0Q3thXsOOG7%2B5aa2wRtObppo00%3DOCQcmniA%40mail.gmail.com.

[Øyvind Harboe]

I've gotten rid of all the warnings from Chisel and Verilator, including the combinational loop warning messages, but the problem persists. I'm working on providing a tiny example(not a technical problem).

On Wednesday, February 22, 2017 at 6:42:31 PM UTC+1, Jack Koenig wrote:

I mention the version number because once this problem is resolved you will probably run into issues with that.

Combinational loops are not allowed in Chisel nor Verilator. So if Verilator is reporting circular logic, that is probably the issue.

On Wed, Feb 22, 2017 at 9:01 AM, Øyvind Harboe <oyvind...@zylin.com> wrote:

I have tried 3.886 as well as 3.900 w same results.

w.r.t. circular logic u32Address, could that be a separate problem?

I am looking into the possibility of stripping down my project and share the code. (not a technical problem).

22. feb. 2017 17:56 skrev "Jack Koenig" <jack.k...@gmail.com>:

While I do not think it is the cause of this issue, chisel3 and firrtl require at least Verilator 3.886 or newer (https://github.com/ucb-bar/firrtl#prerequisites).

The errors seem to be indicating a piece of circular logic in your code. Is u32Address a Wire that gets connected to itself or something?

On Wed, Feb 22, 2017 at 6:59 AM, Stefan Wallentowitz <ste...@wallentowitz.de> wrote:

Hi Øyvind,

On 22.02.2017 15:48, Øyvind Harboe wrote:

>
> system_loaddata-harness.cpp:718:62: error: ‘class Vsystem_loaddata’ has
> no member named
> ‘system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram’
>          sim_data.signals.push_back(new
> VerilatorSData(&(dut->system_loaddata__DOT__Proc__DOT__storer_31_1__DOT__msBackBuffer__DOT__ram__DOT__ram[i])));

Do you have a repo from that I could reproduce it?

Cheers,
Stefan

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[Øyvind Harboe]

Attached is a tiny example that reproduces the error message when you run "sbt run". See error below.

There's not much that can be removed or changed before the problem disappears.

E.g. I switched from the Chisel2 compatibility layer to use chisel3 directly and the problem goes away.

--- a/src/main/scala/doohickey.scala

+++ b/src/main/scala/doohickey.scala

@@ -4,6 +4,6 @@ class doohickey() extends Module {

   val io = new Bundle {

   }

   val bobs = Vec.fill(16) {

-    Module(new thingamabob()).io

+    Module(new thingamabob_chisel3()).io

   }

 }

Error from "sbt run":

doohickey-harness.cpp:115:62: error: ‘class Vdoohickey’ has no member named ‘doohickey__DOT__thingamabob_15_1__DOT___T_23’

         sim_data.signals.push_back(new VerilatorCData(&(dut->doohickey__DOT__thingamabob_15_1__DOT___T_23[i])));

[Donggyu Kim]

This is a bug in chisel testers due to naming changes from newer verilators. We will fix it soon.

[Øyvind Harboe]

Thanks!

I did try with older versions of Verilator, but once I went far enough back, Verilator broke for other reasons.

As a stop-gap, could you point me to the commit in Verilator that introduced the naming changes?

I'd like to try to use a new enough Verilator that works with Chisel, but where I revert the naming change commit.

Cheers,

[Donggyu Kim]

I don't remember what version was working with testers, but I just made a PR: https://github.com/ucb-bar/chisel-testers/pull/112. This should be fine if you are not accessing internal signals.

Thus, a new snapshot will be released once this is merged.

[Øyvind Harboe]

I tried your fix on this bug report https://github.com/ucb-bar/chisel/issues/742, but got another error:

$ sbt run

[output deleted]

make: Entering directory '/home/oyvind/Desktop/verilator_bug/test_run_dir'

make: Leaving directory '/home/oyvind/Desktop/verilator_bug/test_run_dir'

make: *** No rule to make target '/home/oyvind/Desktop/verilator_bug/doohickey-harness.cpp', needed by 'doohickey-harness.o'.  Stop.

[error] (run-main-0) java.lang.AssertionError: assertion failed: 

java.lang.AssertionError: assertion failed: 

at scala.Predef$.assert(Predef.scala:165)

at chisel3.core.assert$.apply(Assert.scala:72)

at chisel3.iotesters.chiselMain$.compile(ChiselMain.scala:77)

at chisel3.iotesters.chiselMain$.chisel3$iotesters$chiselMain$$elaborate(ChiselMain.scala:125)

at chisel3.iotesters.chiselMain$$anonfun$1.apply(ChiselMain.scala:165)

at chisel3.iotesters.chiselMain$$anonfun$1.apply(ChiselMain.scala:165)

at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)

at chisel3.iotesters.chiselMain$.apply(ChiselMain.scala:164)

at main$.main(main.scala:10)

at main.main(main.scala)

[Øyvind Harboe]

There's a problem on the chilsel master branch w.r.t. generating the Vdoohickey.mk file in my example(https://github.com/ucb-bar/chisel/issues/742)

Where is Vdoohickey.mk generated?

This line:

doohickey-harness.o: /home/oyvind/Desktop/verilator_bug/doohickey-harness.cpp

Needs to be changed to:

doohickey-harness.o: /home/oyvind/Desktop/verilator_bug/test_run_dir/doohickey-harness.cpp

[Donggyu Kim]

This is also fixed. A new snapshot will be released this afternoon.

[Øyvind Harboe]

Thanks!

BTW, could the automated tests in these chisel projects on github be run
automatically on all incoming pull-requests?

It would be *great* to build up a large set of regression tests for Chisel
and have them automatically run on *all* incoming pull requests before the
pull-requests are submitted.