[PATCH 0/4] Update AIA drivers in Xvisor as-per latest spec
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Anup Patel
Sep 25, 2022, 1:56:43 PM9/25/22
to xvisor...@googlegroups.com, Anup Patel
This series brings the Xvisor AIA drivers in-sync with latest AIA spec
and corresponding Linux AIA drivers.
These patches can be found in riscv_aia_update_v1 branch at:
https://github.com/avpatel/xvisor-next.git
Anup Patel (4):
RISC-V: Extend ISA string parsing for multi-letter extension names
RISC-V: Remove riscv_aia_available feature flag
DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
arch/riscv/cpu/generic/cpu_init.c | 77 +++++++++---
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 6 +-
arch/riscv/cpu/generic/include/cpu_hwcap.h | 31 +++--
.../cpu/generic/include/riscv_encoding.h | 24 +---
drivers/irqchip/irq-riscv-imsic.c | 116 +++++++++++++-----
drivers/irqchip/irq-riscv-intc.c | 8 +-
6 files changed, 177 insertions(+), 85 deletions(-)
--
2.34.1
and corresponding Linux AIA drivers.
These patches can be found in riscv_aia_update_v1 branch at:
https://github.com/avpatel/xvisor-next.git
Anup Patel (4):
RISC-V: Extend ISA string parsing for multi-letter extension names
RISC-V: Remove riscv_aia_available feature flag
DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
arch/riscv/cpu/generic/cpu_init.c | 77 +++++++++---
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 6 +-
arch/riscv/cpu/generic/include/cpu_hwcap.h | 31 +++--
.../cpu/generic/include/riscv_encoding.h | 24 +---
drivers/irqchip/irq-riscv-imsic.c | 116 +++++++++++++-----
drivers/irqchip/irq-riscv-intc.c | 8 +-
6 files changed, 177 insertions(+), 85 deletions(-)
--
2.34.1
Anup Patel
Sep 25, 2022, 1:56:46 PM9/25/22
to xvisor...@googlegroups.com, Anup Patel
We have a lot of multi-letter extension names defined in past 1-2 years
so let us exted the ISA string parsing to detect such extensions.
To start with, we will detect only smaia and ssaia extensions since
these are defined by the latest AIA specification.
Signed-off-by: Anup Patel <apa...@ventanamicro.com>
---
arch/riscv/cpu/generic/cpu_init.c | 66 +++++++++++++++++++---
arch/riscv/cpu/generic/include/cpu_hwcap.h | 28 +++++++--
2 files changed, 81 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu_init.c b/arch/riscv/cpu/generic/cpu_init.c
index 8c2cd663..a402fe14 100644
--- a/arch/riscv/cpu/generic/cpu_init.c
+++ b/arch/riscv/cpu/generic/cpu_init.c
@@ -88,21 +88,34 @@ int riscv_isa_populate_string(unsigned long xlen,
if (!out || (out_sz < 16))
return VMM_EINVALID;
+ memset(out, 0, out_sz);
+
if (xlen == 32)
- vmm_snprintf(out, sizeof(out_sz), "rv%d", 32);
+ vmm_snprintf(out, out_sz, "rv%d", 32);
else if (xlen == 64)
- vmm_snprintf(out, sizeof(out_sz), "rv%d", 64);
+ vmm_snprintf(out, out_sz, "rv%d", 64);
else
return VMM_EINVALID;
pos = strlen(out);
valid_isa_len = strlen(valid_isa_order);
- for (i = 0; i < valid_isa_len; i++) {
+ for (i = 0; (i < valid_isa_len) && (pos < (out_sz - 1)); i++) {
index = valid_isa_order[i] - 'A';
- if ((bmap[0] & BIT_MASK(index)) && (pos < (out_sz - 1)))
+ if (test_bit(index, bmap) && (pos < (out_sz - 1)))
out[pos++] = 'a' + index;
}
- out[pos] = '\0';
+
+#define SET_ISA_EXT_MAP(name, bit) \
+ do { \
+ if (test_bit(bit, bmap)) { \
+ strncat(&out[pos], "_" name, out_sz - pos - 1); \
+ pos += strlen("_" name); \
+ } \
+ } while (false) \
+
+ SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
+#undef SET_ISA_EXT_MAP
return VMM_OK;
}
@@ -112,7 +125,8 @@ int riscv_isa_parse_string(const char *isa,
unsigned long *out_bitmap,
size_t out_bitmap_sz)
{
- size_t i, isa_len;
+ size_t i, j, isa_len;
+ char mstr[RISCV_ISA_EXT_NAME_LEN_MAX];
if (!isa || !out_xlen || !out_bitmap ||
(out_bitmap_sz < __riscv_xlen))
@@ -144,13 +158,49 @@ int riscv_isa_parse_string(const char *isa,
return VMM_EINVALID;
}
- for (; i < isa_len; ++i) {
+ for (; i < isa_len; i++) {
+ if (isa[i] == '_')
+ break;
+
if ('a' <= isa[i] && isa[i] <= 'z')
__set_bit(isa[i] - 'a', out_bitmap);
if ('A' <= isa[i] && isa[i] <= 'Z')
__set_bit(isa[i] - 'A', out_bitmap);
}
+ while (i < isa_len) {
+ if (isa[i] != '_') {
+ i++;
+ continue;
+ }
+
+ /* Skip the '_' character */
+ i++;
+
+ /* Extract the multi-letter extension name */
+ j = 0;
+ while ((i < isa_len) && (isa[i] != '_') &&
+ (j < (sizeof(mstr) - 1)))
+ mstr[j++] = isa[i++];
+ mstr[j] = '\0';
+
+ /* Skip empty multi-letter extension name */
+ if (!j)
+ continue;
+
+#define SET_ISA_EXT_MAP(name, bit) \
+ do { \
+ if (!strcmp(mstr, name)) { \
+ __set_bit(bit, out_bitmap); \
+ continue; \
+ } \
+ } while (false) \
+
+ SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
+#undef SET_ISA_EXT_MAP
+ }
+
return VMM_OK;
}
@@ -354,7 +404,7 @@ void arch_cpu_print(struct vmm_chardev *cdev, u32 cpu)
void arch_cpu_print_summary(struct vmm_chardev *cdev)
{
- char isa[128];
+ char isa[256];
#ifdef CONFIG_64BIT
riscv_isa_populate_string(64, NULL, isa, sizeof(isa));
#else
diff --git a/arch/riscv/cpu/generic/include/cpu_hwcap.h b/arch/riscv/cpu/generic/include/cpu_hwcap.h
index c7c87829..2bdaed1d 100644
--- a/arch/riscv/cpu/generic/include/cpu_hwcap.h
+++ b/arch/riscv/cpu/generic/include/cpu_hwcap.h
@@ -37,12 +37,30 @@
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
-#define RISCV_ISA_EXT_zicsr (('z' - 'a') + 1)
-#define RISCV_ISA_EXT_zifencei (('z' - 'a') + 2)
-#define RISCV_ISA_EXT_zam (('z' - 'a') + 3)
-#define RISCV_ISA_EXT_ztso (('z' - 'a') + 4)
+/*
+ * Increse this to higher value as kernel support more ISA extensions.
+ */
+#define RISCV_ISA_EXT_MAX 64
+#define RISCV_ISA_EXT_NAME_LEN_MAX 32
+
+/* The base ID for multi-letter ISA extensions */
+#define RISCV_ISA_EXT_BASE 26
+
+/*
+ * This enum represent the logical ID for each multi-letter
+ * RISC-V ISA extension. The logical ID should start from
+ * RISCV_ISA_EXT_BASE and must not exceed RISCV_ISA_EXT_MAX.
+ * 0-25 range is reserved for single letter extensions while
+ * all the multi-letter extensions should define the next
+ * available logical extension id.
+ */
+enum riscv_isa_ext_id {
+ RISCV_ISA_EXT_SSAIA = RISCV_ISA_EXT_BASE,
+ RISCV_ISA_EXT_SMAIA,
+ RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
+};
-#define RISCV_ISA_EXT_MAX 256
+#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
struct vmm_devtree_node;
--
2.34.1
so let us exted the ISA string parsing to detect such extensions.
To start with, we will detect only smaia and ssaia extensions since
these are defined by the latest AIA specification.
Signed-off-by: Anup Patel <apa...@ventanamicro.com>
---
arch/riscv/cpu/generic/cpu_init.c | 66 +++++++++++++++++++---
arch/riscv/cpu/generic/include/cpu_hwcap.h | 28 +++++++--
2 files changed, 81 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu_init.c b/arch/riscv/cpu/generic/cpu_init.c
index 8c2cd663..a402fe14 100644
--- a/arch/riscv/cpu/generic/cpu_init.c
+++ b/arch/riscv/cpu/generic/cpu_init.c
@@ -88,21 +88,34 @@ int riscv_isa_populate_string(unsigned long xlen,
if (!out || (out_sz < 16))
return VMM_EINVALID;
+ memset(out, 0, out_sz);
+
if (xlen == 32)
- vmm_snprintf(out, sizeof(out_sz), "rv%d", 32);
+ vmm_snprintf(out, out_sz, "rv%d", 32);
else if (xlen == 64)
- vmm_snprintf(out, sizeof(out_sz), "rv%d", 64);
+ vmm_snprintf(out, out_sz, "rv%d", 64);
else
return VMM_EINVALID;
pos = strlen(out);
valid_isa_len = strlen(valid_isa_order);
- for (i = 0; i < valid_isa_len; i++) {
+ for (i = 0; (i < valid_isa_len) && (pos < (out_sz - 1)); i++) {
index = valid_isa_order[i] - 'A';
- if ((bmap[0] & BIT_MASK(index)) && (pos < (out_sz - 1)))
+ if (test_bit(index, bmap) && (pos < (out_sz - 1)))
out[pos++] = 'a' + index;
}
- out[pos] = '\0';
+
+#define SET_ISA_EXT_MAP(name, bit) \
+ do { \
+ if (test_bit(bit, bmap)) { \
+ strncat(&out[pos], "_" name, out_sz - pos - 1); \
+ pos += strlen("_" name); \
+ } \
+ } while (false) \
+
+ SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
+#undef SET_ISA_EXT_MAP
return VMM_OK;
}
@@ -112,7 +125,8 @@ int riscv_isa_parse_string(const char *isa,
unsigned long *out_bitmap,
size_t out_bitmap_sz)
{
- size_t i, isa_len;
+ size_t i, j, isa_len;
+ char mstr[RISCV_ISA_EXT_NAME_LEN_MAX];
if (!isa || !out_xlen || !out_bitmap ||
(out_bitmap_sz < __riscv_xlen))
@@ -144,13 +158,49 @@ int riscv_isa_parse_string(const char *isa,
return VMM_EINVALID;
}
- for (; i < isa_len; ++i) {
+ for (; i < isa_len; i++) {
+ if (isa[i] == '_')
+ break;
+
if ('a' <= isa[i] && isa[i] <= 'z')
__set_bit(isa[i] - 'a', out_bitmap);
if ('A' <= isa[i] && isa[i] <= 'Z')
__set_bit(isa[i] - 'A', out_bitmap);
}
+ while (i < isa_len) {
+ if (isa[i] != '_') {
+ i++;
+ continue;
+ }
+
+ /* Skip the '_' character */
+ i++;
+
+ /* Extract the multi-letter extension name */
+ j = 0;
+ while ((i < isa_len) && (isa[i] != '_') &&
+ (j < (sizeof(mstr) - 1)))
+ mstr[j++] = isa[i++];
+ mstr[j] = '\0';
+
+ /* Skip empty multi-letter extension name */
+ if (!j)
+ continue;
+
+#define SET_ISA_EXT_MAP(name, bit) \
+ do { \
+ if (!strcmp(mstr, name)) { \
+ __set_bit(bit, out_bitmap); \
+ continue; \
+ } \
+ } while (false) \
+
+ SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
+#undef SET_ISA_EXT_MAP
+ }
+
return VMM_OK;
}
@@ -354,7 +404,7 @@ void arch_cpu_print(struct vmm_chardev *cdev, u32 cpu)
void arch_cpu_print_summary(struct vmm_chardev *cdev)
{
- char isa[128];
+ char isa[256];
#ifdef CONFIG_64BIT
riscv_isa_populate_string(64, NULL, isa, sizeof(isa));
#else
diff --git a/arch/riscv/cpu/generic/include/cpu_hwcap.h b/arch/riscv/cpu/generic/include/cpu_hwcap.h
index c7c87829..2bdaed1d 100644
--- a/arch/riscv/cpu/generic/include/cpu_hwcap.h
+++ b/arch/riscv/cpu/generic/include/cpu_hwcap.h
@@ -37,12 +37,30 @@
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
-#define RISCV_ISA_EXT_zicsr (('z' - 'a') + 1)
-#define RISCV_ISA_EXT_zifencei (('z' - 'a') + 2)
-#define RISCV_ISA_EXT_zam (('z' - 'a') + 3)
-#define RISCV_ISA_EXT_ztso (('z' - 'a') + 4)
+/*
+ * Increse this to higher value as kernel support more ISA extensions.
+ */
+#define RISCV_ISA_EXT_MAX 64
+#define RISCV_ISA_EXT_NAME_LEN_MAX 32
+
+/* The base ID for multi-letter ISA extensions */
+#define RISCV_ISA_EXT_BASE 26
+
+/*
+ * This enum represent the logical ID for each multi-letter
+ * RISC-V ISA extension. The logical ID should start from
+ * RISCV_ISA_EXT_BASE and must not exceed RISCV_ISA_EXT_MAX.
+ * 0-25 range is reserved for single letter extensions while
+ * all the multi-letter extensions should define the next
+ * available logical extension id.
+ */
+enum riscv_isa_ext_id {
+ RISCV_ISA_EXT_SSAIA = RISCV_ISA_EXT_BASE,
+ RISCV_ISA_EXT_SMAIA,
+ RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
+};
-#define RISCV_ISA_EXT_MAX 256
+#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
struct vmm_devtree_node;
--
2.34.1
Anup Patel
Sep 25, 2022, 1:56:48 PM9/25/22
to xvisor...@googlegroups.com, Anup Patel
The latest AIA specification defines ISA extension names for AIA CSRs
so we should use these new ISA names instead of a riscv_aia_available
feature flag.
arch/riscv/cpu/generic/cpu_init.c | 11 +----------
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 6 +++---
arch/riscv/cpu/generic/include/cpu_hwcap.h | 3 ---
drivers/irqchip/irq-riscv-imsic.c | 2 +-
drivers/irqchip/irq-riscv-intc.c | 8 +++++---
5 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu_init.c b/arch/riscv/cpu/generic/cpu_init.c
index a402fe14..0be32648 100644
--- a/arch/riscv/cpu/generic/cpu_init.c
+++ b/arch/riscv/cpu/generic/cpu_init.c
@@ -231,12 +231,11 @@ unsigned long riscv_stage2_vmid_bits = 0;
unsigned long riscv_stage2_vmid_nested = 0;
bool riscv_stage2_use_vmid = false;
unsigned long riscv_timer_hz = 0;
-bool riscv_aia_available = true;
int __init arch_cpu_nascent_init(void)
{
DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
- struct vmm_devtree_node *dn, *in, *cpus;
+ struct vmm_devtree_node *dn, *cpus;
const char *isa, *str;
unsigned long val, this_xlen;
int rc = VMM_OK;
@@ -298,14 +297,6 @@ int __init arch_cpu_nascent_init(void)
break;
}
- in = vmm_devtree_find_compatible(dn, NULL,
- "riscv,cpu-intc-aia");
- if (!in) {
- riscv_aia_available = false;
- } else {
- vmm_devtree_dref_node(in);
- }
-
if (riscv_xlen) {
if (riscv_xlen != this_xlen ||
riscv_xlen != __riscv_xlen) {
diff --git a/arch/riscv/cpu/generic/cpu_vcpu_helper.c b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
index 60eda0fa..da8f9ecd 100644
--- a/arch/riscv/cpu/generic/cpu_vcpu_helper.c
+++ b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
@@ -288,7 +288,7 @@ int arch_vcpu_init(struct vmm_vcpu *vcpu)
riscv_priv(vcpu)->isa[0] &= RISCV_ISA_ALLOWED;
/* H-extension only available when AIA CSRs are available */
- if (!riscv_aia_available) {
+ if (!riscv_isa_extension_available(NULL, SxAIA)) {
riscv_priv(vcpu)->isa[0] &=
~riscv_isa_extension_mask(h);
}
@@ -451,7 +451,7 @@ void cpu_vcpu_irq_deleg_update(struct vmm_vcpu *vcpu, bool nested_virt)
csr_write(CSR_HIDELEG, 0);
/* Enable sip/siph and sie/sieh trapping */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
csr_set(CSR_HVICTL, HVICTL_VTI);
}
} else {
@@ -459,7 +459,7 @@ void cpu_vcpu_irq_deleg_update(struct vmm_vcpu *vcpu, bool nested_virt)
csr_write(CSR_HIDELEG, HIDELEG_DEFAULT);
/* Disable sip/siph and sie/sieh trapping */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
csr_clear(CSR_HVICTL, HVICTL_VTI);
}
}
diff --git a/arch/riscv/cpu/generic/include/cpu_hwcap.h b/arch/riscv/cpu/generic/include/cpu_hwcap.h
index 2bdaed1d..3fda16ed 100644
--- a/arch/riscv/cpu/generic/include/cpu_hwcap.h
+++ b/arch/riscv/cpu/generic/include/cpu_hwcap.h
@@ -146,7 +146,4 @@ extern unsigned long riscv_stage2_vmid_nested;
/** RISC-V Time Base Frequency */
extern unsigned long riscv_timer_hz;
-/** RISC-V AIA CSRs available */
-extern bool riscv_aia_available;
-
#endif
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index e6d9a04b..70e8cc11 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -775,7 +775,7 @@ static int __init imsic_init(struct vmm_devtree_node *node)
return VMM_ENODEV;
}
- if (!riscv_aia_available) {
+ if (!riscv_isa_extension_available(NULL, SxAIA)) {
vmm_lerror(node->name, "AIA support not available\n");
return VMM_ENODEV;
}
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 4e34f184..2cceade3 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -123,7 +123,7 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
/* Determine number of IRQs */
nr_irqs = BITS_PER_LONG;
- if (riscv_aia_available && BITS_PER_LONG == 32)
+ if (riscv_isa_extension_available(NULL, SxAIA) && BITS_PER_LONG == 32)
nr_irqs = nr_irqs * 2;
/* Register IRQ domain */
@@ -156,7 +156,7 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
}
/* Register active IRQ callback */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
vmm_host_irq_set_active_callback(riscv_intc_aia_active_irq);
} else {
vmm_host_irq_set_active_callback(riscv_intc_active_irq);
@@ -164,7 +164,9 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
/* Announce RISC-V INTC */
vmm_init_printf("riscv-intc: registered %d local interrupts%s\n",
- nr_irqs, (riscv_aia_available) ? " with AIA" : "");
+ nr_irqs,
+ (riscv_isa_extension_available(NULL, SxAIA)) ?
+ " with AIA" : "");
return VMM_OK;
}
--
2.34.1
so we should use these new ISA names instead of a riscv_aia_available
feature flag.
arch/riscv/cpu/generic/cpu_init.c | 11 +----------
arch/riscv/cpu/generic/cpu_vcpu_helper.c | 6 +++---
arch/riscv/cpu/generic/include/cpu_hwcap.h | 3 ---
drivers/irqchip/irq-riscv-imsic.c | 2 +-
drivers/irqchip/irq-riscv-intc.c | 8 +++++---
5 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu_init.c b/arch/riscv/cpu/generic/cpu_init.c
index a402fe14..0be32648 100644
--- a/arch/riscv/cpu/generic/cpu_init.c
+++ b/arch/riscv/cpu/generic/cpu_init.c
@@ -231,12 +231,11 @@ unsigned long riscv_stage2_vmid_bits = 0;
unsigned long riscv_stage2_vmid_nested = 0;
bool riscv_stage2_use_vmid = false;
unsigned long riscv_timer_hz = 0;
-bool riscv_aia_available = true;
int __init arch_cpu_nascent_init(void)
{
DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
- struct vmm_devtree_node *dn, *in, *cpus;
+ struct vmm_devtree_node *dn, *cpus;
const char *isa, *str;
unsigned long val, this_xlen;
int rc = VMM_OK;
@@ -298,14 +297,6 @@ int __init arch_cpu_nascent_init(void)
break;
}
- in = vmm_devtree_find_compatible(dn, NULL,
- "riscv,cpu-intc-aia");
- if (!in) {
- riscv_aia_available = false;
- } else {
- vmm_devtree_dref_node(in);
- }
-
if (riscv_xlen) {
if (riscv_xlen != this_xlen ||
riscv_xlen != __riscv_xlen) {
diff --git a/arch/riscv/cpu/generic/cpu_vcpu_helper.c b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
index 60eda0fa..da8f9ecd 100644
--- a/arch/riscv/cpu/generic/cpu_vcpu_helper.c
+++ b/arch/riscv/cpu/generic/cpu_vcpu_helper.c
@@ -288,7 +288,7 @@ int arch_vcpu_init(struct vmm_vcpu *vcpu)
riscv_priv(vcpu)->isa[0] &= RISCV_ISA_ALLOWED;
/* H-extension only available when AIA CSRs are available */
- if (!riscv_aia_available) {
+ if (!riscv_isa_extension_available(NULL, SxAIA)) {
riscv_priv(vcpu)->isa[0] &=
~riscv_isa_extension_mask(h);
}
@@ -451,7 +451,7 @@ void cpu_vcpu_irq_deleg_update(struct vmm_vcpu *vcpu, bool nested_virt)
csr_write(CSR_HIDELEG, 0);
/* Enable sip/siph and sie/sieh trapping */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
csr_set(CSR_HVICTL, HVICTL_VTI);
}
} else {
@@ -459,7 +459,7 @@ void cpu_vcpu_irq_deleg_update(struct vmm_vcpu *vcpu, bool nested_virt)
csr_write(CSR_HIDELEG, HIDELEG_DEFAULT);
/* Disable sip/siph and sie/sieh trapping */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
csr_clear(CSR_HVICTL, HVICTL_VTI);
}
}
diff --git a/arch/riscv/cpu/generic/include/cpu_hwcap.h b/arch/riscv/cpu/generic/include/cpu_hwcap.h
index 2bdaed1d..3fda16ed 100644
--- a/arch/riscv/cpu/generic/include/cpu_hwcap.h
+++ b/arch/riscv/cpu/generic/include/cpu_hwcap.h
@@ -146,7 +146,4 @@ extern unsigned long riscv_stage2_vmid_nested;
/** RISC-V Time Base Frequency */
extern unsigned long riscv_timer_hz;
-/** RISC-V AIA CSRs available */
-extern bool riscv_aia_available;
-
#endif
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index e6d9a04b..70e8cc11 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -775,7 +775,7 @@ static int __init imsic_init(struct vmm_devtree_node *node)
return VMM_ENODEV;
}
- if (!riscv_aia_available) {
+ if (!riscv_isa_extension_available(NULL, SxAIA)) {
vmm_lerror(node->name, "AIA support not available\n");
return VMM_ENODEV;
}
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 4e34f184..2cceade3 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -123,7 +123,7 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
/* Determine number of IRQs */
nr_irqs = BITS_PER_LONG;
- if (riscv_aia_available && BITS_PER_LONG == 32)
+ if (riscv_isa_extension_available(NULL, SxAIA) && BITS_PER_LONG == 32)
nr_irqs = nr_irqs * 2;
/* Register IRQ domain */
@@ -156,7 +156,7 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
}
/* Register active IRQ callback */
- if (riscv_aia_available) {
+ if (riscv_isa_extension_available(NULL, SxAIA)) {
vmm_host_irq_set_active_callback(riscv_intc_aia_active_irq);
} else {
vmm_host_irq_set_active_callback(riscv_intc_active_irq);
@@ -164,7 +164,9 @@ static int __init riscv_intc_init(struct vmm_devtree_node *node)
/* Announce RISC-V INTC */
vmm_init_printf("riscv-intc: registered %d local interrupts%s\n",
- nr_irqs, (riscv_aia_available) ? " with AIA" : "");
+ nr_irqs,
+ (riscv_isa_extension_available(NULL, SxAIA)) ?
+ " with AIA" : "");
return VMM_OK;
}
--
2.34.1
Anup Patel
Sep 25, 2022, 1:56:50 PM9/25/22
to xvisor...@googlegroups.com, Anup Patel
The [m|s|vs]seteipnum and [m|s|vs]clreipnum CSRs are removed from the
latest stable AIA specification so let us remove the use of these CSRs
from IMSIC driver.
.../cpu/generic/include/riscv_encoding.h | 24 +------
drivers/irqchip/irq-riscv-imsic.c | 69 ++++++++++++++++---
2 files changed, 63 insertions(+), 30 deletions(-)
diff --git a/arch/riscv/cpu/generic/include/riscv_encoding.h b/arch/riscv/cpu/generic/include/riscv_encoding.h
index 1124d4ba..5e85eaef 100644
--- a/arch/riscv/cpu/generic/include/riscv_encoding.h
+++ b/arch/riscv/cpu/generic/include/riscv_encoding.h
@@ -481,14 +481,8 @@
#define CSR_SIREG 0x151
/* Supervisor-Level Interrupts (AIA) */
-#define CSR_STOPI 0xdb0
-
-/* Supervisor-Level IMSIC Interface (AIA) */
-#define CSR_SSETEIPNUM 0x158
-#define CSR_SCLREIPNUM 0x159
-#define CSR_SSETEIENUM 0x15a
-#define CSR_SCLREIENUM 0x15b
#define CSR_STOPEI 0x15c
+#define CSR_STOPI 0xdb0
/* Supervisor-Level High-Half CSRs (AIA) */
#define CSR_SIEH 0x114
@@ -550,14 +544,8 @@
#define CSR_VSIREG 0x251
/* VS-Level Interrupts (H-extension with AIA) */
-#define CSR_VSTOPI 0xeb0
-
-/* VS-Level IMSIC Interface (H-extension with AIA) */
-#define CSR_VSSETEIPNUM 0x258
-#define CSR_VSCLREIPNUM 0x259
-#define CSR_VSSETEIENUM 0x25a
-#define CSR_VSCLREIENUM 0x25b
#define CSR_VSTOPEI 0x25c
+#define CSR_VSTOPI 0xeb0
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
#define CSR_HIDELEGH 0x613
@@ -825,14 +813,8 @@
#define CSR_MIREG 0x351
/* Machine-Level Interrupts (AIA) */
-#define CSR_MTOPI 0xfb0
-
-/* Machine-Level IMSIC Interface (AIA) */
-#define CSR_MSETEIPNUM 0x358
-#define CSR_MCLREIPNUM 0x359
-#define CSR_MSETEIENUM 0x35a
-#define CSR_MCLREIENUM 0x35b
#define CSR_MTOPEI 0x35c
+#define CSR_MTOPI 0xfb0
/* Virtual Interrupts for Supervisor Level (AIA) */
#define CSR_MVIEN 0x308
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index 70e8cc11..c7a117e7 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -49,19 +49,31 @@
#define IMSIC_ENABLE_EITHRESHOLD 0
#define imsic_csr_write(__c, __v) \
-do { \
- csr_write(CSR_SISELECT, __c); \
- csr_write(CSR_SIREG, __v); \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_write(CSR_SIREG, __v); \
} while (0)
-#define imsic_csr_read(__c) \
-({ \
- unsigned long __v; \
- csr_write(CSR_SISELECT, __c); \
- __v = csr_read(CSR_SIREG); \
- __v; \
+#define imsic_csr_read(__c) \
+({ \
+ unsigned long __v; \
+ csr_write(CSR_SISELECT, __c); \
+ __v = csr_read(CSR_SIREG); \
+ __v; \
})
+#define imsic_csr_set(__c, __v) \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_set(CSR_SIREG, __v); \
+} while (0)
+
+#define imsic_csr_clear(__c, __v) \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_clear(CSR_SIREG, __v); \
+} while (0)
+
struct imsic_mmio {
physical_addr_t pa;
void *va;
@@ -226,6 +238,45 @@ static inline void __imsic_id_disable(unsigned int id)
csr_write(CSR_SCLREIENUM, id);
}
+static void __imsic_eix_update(unsigned long base_id,
+ unsigned long num_id, bool pend, bool val)
+{
+ irq_flags_t flags;
+ unsigned long i, isel, ireg;
+ unsigned long id = base_id, last_id = base_id + num_id;
+
+ while (id < last_id) {
+ isel = id / BITS_PER_LONG;
+ isel *= BITS_PER_LONG / IMSIC_EIPx_BITS;
+ isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0;
+
+ ireg = 0;
+ for (i = id & (__riscv_xlen - 1);
+ (id < last_id) && (i < __riscv_xlen); i++) {
+ ireg |= BIT(i);
+ id++;
+ }
+
+ /*
+ * The IMSIC EIEx and EIPx registers are indirectly
+ * accessed via using ISELECT and IREG CSRs so we
+ * save/restore local IRQ to ensure that we don't
+ * get preempted while accessing IMSIC registers.
+ */
+ arch_cpu_irq_save(flags);
+ if (val)
+ imsic_csr_set(isel, ireg);
+ else
+ imsic_csr_clear(isel, ireg);
+ arch_cpu_irq_restore(flags);
+ }
+}
+
+#define __imsic_id_enable(__id) \
+ __imsic_eix_update((__id), 1, false, true)
+#define __imsic_id_disable(__id) \
+ __imsic_eix_update((__id), 1, false, false)
+
#ifdef CONFIG_SMP
static void __imsic_id_smp_sync(struct imsic_priv *priv)
{
--
2.34.1
latest stable AIA specification so let us remove the use of these CSRs
from IMSIC driver.
.../cpu/generic/include/riscv_encoding.h | 24 +------
drivers/irqchip/irq-riscv-imsic.c | 69 ++++++++++++++++---
2 files changed, 63 insertions(+), 30 deletions(-)
diff --git a/arch/riscv/cpu/generic/include/riscv_encoding.h b/arch/riscv/cpu/generic/include/riscv_encoding.h
index 1124d4ba..5e85eaef 100644
--- a/arch/riscv/cpu/generic/include/riscv_encoding.h
+++ b/arch/riscv/cpu/generic/include/riscv_encoding.h
@@ -481,14 +481,8 @@
#define CSR_SIREG 0x151
/* Supervisor-Level Interrupts (AIA) */
-#define CSR_STOPI 0xdb0
-
-/* Supervisor-Level IMSIC Interface (AIA) */
-#define CSR_SSETEIPNUM 0x158
-#define CSR_SCLREIPNUM 0x159
-#define CSR_SSETEIENUM 0x15a
-#define CSR_SCLREIENUM 0x15b
#define CSR_STOPEI 0x15c
+#define CSR_STOPI 0xdb0
/* Supervisor-Level High-Half CSRs (AIA) */
#define CSR_SIEH 0x114
@@ -550,14 +544,8 @@
#define CSR_VSIREG 0x251
/* VS-Level Interrupts (H-extension with AIA) */
-#define CSR_VSTOPI 0xeb0
-
-/* VS-Level IMSIC Interface (H-extension with AIA) */
-#define CSR_VSSETEIPNUM 0x258
-#define CSR_VSCLREIPNUM 0x259
-#define CSR_VSSETEIENUM 0x25a
-#define CSR_VSCLREIENUM 0x25b
#define CSR_VSTOPEI 0x25c
+#define CSR_VSTOPI 0xeb0
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
#define CSR_HIDELEGH 0x613
@@ -825,14 +813,8 @@
#define CSR_MIREG 0x351
/* Machine-Level Interrupts (AIA) */
-#define CSR_MTOPI 0xfb0
-
-/* Machine-Level IMSIC Interface (AIA) */
-#define CSR_MSETEIPNUM 0x358
-#define CSR_MCLREIPNUM 0x359
-#define CSR_MSETEIENUM 0x35a
-#define CSR_MCLREIENUM 0x35b
#define CSR_MTOPEI 0x35c
+#define CSR_MTOPI 0xfb0
/* Virtual Interrupts for Supervisor Level (AIA) */
#define CSR_MVIEN 0x308
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index 70e8cc11..c7a117e7 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -49,19 +49,31 @@
#define IMSIC_ENABLE_EITHRESHOLD 0
#define imsic_csr_write(__c, __v) \
-do { \
- csr_write(CSR_SISELECT, __c); \
- csr_write(CSR_SIREG, __v); \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_write(CSR_SIREG, __v); \
} while (0)
-#define imsic_csr_read(__c) \
-({ \
- unsigned long __v; \
- csr_write(CSR_SISELECT, __c); \
- __v = csr_read(CSR_SIREG); \
- __v; \
+#define imsic_csr_read(__c) \
+({ \
+ unsigned long __v; \
+ csr_write(CSR_SISELECT, __c); \
+ __v = csr_read(CSR_SIREG); \
+ __v; \
})
+#define imsic_csr_set(__c, __v) \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_set(CSR_SIREG, __v); \
+} while (0)
+
+#define imsic_csr_clear(__c, __v) \
+do { \
+ csr_write(CSR_SISELECT, __c); \
+ csr_clear(CSR_SIREG, __v); \
+} while (0)
+
struct imsic_mmio {
physical_addr_t pa;
void *va;
@@ -226,6 +238,45 @@ static inline void __imsic_id_disable(unsigned int id)
csr_write(CSR_SCLREIENUM, id);
}
+static void __imsic_eix_update(unsigned long base_id,
+ unsigned long num_id, bool pend, bool val)
+{
+ irq_flags_t flags;
+ unsigned long i, isel, ireg;
+ unsigned long id = base_id, last_id = base_id + num_id;
+
+ while (id < last_id) {
+ isel = id / BITS_PER_LONG;
+ isel *= BITS_PER_LONG / IMSIC_EIPx_BITS;
+ isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0;
+
+ ireg = 0;
+ for (i = id & (__riscv_xlen - 1);
+ (id < last_id) && (i < __riscv_xlen); i++) {
+ ireg |= BIT(i);
+ id++;
+ }
+
+ /*
+ * The IMSIC EIEx and EIPx registers are indirectly
+ * accessed via using ISELECT and IREG CSRs so we
+ * save/restore local IRQ to ensure that we don't
+ * get preempted while accessing IMSIC registers.
+ */
+ arch_cpu_irq_save(flags);
+ if (val)
+ imsic_csr_set(isel, ireg);
+ else
+ imsic_csr_clear(isel, ireg);
+ arch_cpu_irq_restore(flags);
+ }
+}
+
+#define __imsic_id_enable(__id) \
+ __imsic_eix_update((__id), 1, false, true)
+#define __imsic_id_disable(__id) \
+ __imsic_eix_update((__id), 1, false, false)
+
#ifdef CONFIG_SMP
static void __imsic_id_smp_sync(struct imsic_priv *priv)
{
--
2.34.1
Anup Patel
Sep 25, 2022, 1:56:53 PM9/25/22
to xvisor...@googlegroups.com, Anup Patel
The riscv,ipi-id DT property has been replaced with riscv,slow-ipi
boolean DT property. This means instead of explicitly specifying
IMSIC ID to be used for IPIs, we let IMSIC driver choose the IPI
IMSIC ID when riscv,slow-ipi DT property is not set (or absent).
drivers/irqchip/irq-riscv-imsic.c | 45 ++++++++++++++++---------------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index c7a117e7..878f5d4d 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -98,6 +98,7 @@ struct imsic_priv {
struct vmm_cpumask lmask;
/* IPI domain */
+ bool slow_ipi;
u32 ipi_id;
u32 ipi_lsync_id;
struct vmm_host_irqdomain *ipi_domain;
@@ -502,17 +503,17 @@ static void imsic_ipi_disable(struct imsic_priv *priv)
static int __init imsic_ipi_domain_init(struct imsic_priv *priv)
{
- int rc;
+ int virq;
- /* Do nothing if IPI interrupt identity not available */
- if (!priv->ipi_id) {
+ /* Skip IPI setup if IPIs are slow */
+ if (priv->slow_ipi)
goto skip_ipi;
- }
- /* Sanity check on IPI interrupt identity */
- if (priv->global.nr_ids < priv->ipi_id) {
- return VMM_EINVALID;
- }
+ /* Allocate interrupt identity for IPIs */
+ virq = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
+ if (virq < 0)
+ return virq;
+ priv->ipi_id = virq;
/* Reserve interrupt identity for IPI */
bitmap_set(priv->ids_used_bimap, priv->ipi_id, 1);
@@ -522,28 +523,28 @@ static int __init imsic_ipi_domain_init(struct imsic_priv *priv)
1, &imsic_ipi_domain_ops,
priv);
if (!priv->ipi_domain) {
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
return VMM_ENOMEM;
}
/* Pre-create IPI mappings */
- rc = vmm_host_irqdomain_create_mapping(priv->ipi_domain, 0);
- if (rc < 0) {
+ virq = vmm_host_irqdomain_create_mapping(priv->ipi_domain, 0);
+ if (virq < 0) {
vmm_lerror("imsic", "failed to create IPI mapping\n");
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
- return rc;
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
+ return virq;
}
skip_ipi:
/* Allocate interrupt identity for local enable/disable sync */
- rc = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
- if (rc < 0) {
+ virq = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
+ if (virq < 0) {
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
- return rc;
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
+ return virq;
}
- priv->ipi_lsync_id = rc;
+ priv->ipi_lsync_id = virq;
return VMM_OK;
}
@@ -552,7 +553,7 @@ static void __init imsic_ipi_domain_cleanup(struct imsic_priv *priv)
{
imsic_ids_free(priv, priv->ipi_lsync_id, get_count_order(1));
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
}
#else
static void imsic_ipi_enable(struct imsic_priv *priv)
@@ -914,9 +915,9 @@ static int __init imsic_init(struct vmm_devtree_node *node)
return VMM_EINVALID;
}
- /* Find interrupt indentity to be used for IPI */
- if (vmm_devtree_read_u32(node, "riscv,ipi-id", &priv->ipi_id))
- priv->ipi_id = 0;
+ /* Check if IPIs are slow */
+ priv->slow_ipi = vmm_devtree_getattr(node, "riscv,slow-ipi") ?
+ TRUE : FALSE;
/* Compute base address */
rc = vmm_devtree_regaddr(node, &global->base_addr, 0);
--
2.34.1
boolean DT property. This means instead of explicitly specifying
IMSIC ID to be used for IPIs, we let IMSIC driver choose the IPI
IMSIC ID when riscv,slow-ipi DT property is not set (or absent).
drivers/irqchip/irq-riscv-imsic.c | 45 ++++++++++++++++---------------
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c
index c7a117e7..878f5d4d 100644
--- a/drivers/irqchip/irq-riscv-imsic.c
+++ b/drivers/irqchip/irq-riscv-imsic.c
@@ -98,6 +98,7 @@ struct imsic_priv {
struct vmm_cpumask lmask;
/* IPI domain */
+ bool slow_ipi;
u32 ipi_id;
u32 ipi_lsync_id;
struct vmm_host_irqdomain *ipi_domain;
@@ -502,17 +503,17 @@ static void imsic_ipi_disable(struct imsic_priv *priv)
static int __init imsic_ipi_domain_init(struct imsic_priv *priv)
{
- int rc;
+ int virq;
- /* Do nothing if IPI interrupt identity not available */
- if (!priv->ipi_id) {
+ /* Skip IPI setup if IPIs are slow */
+ if (priv->slow_ipi)
goto skip_ipi;
- }
- /* Sanity check on IPI interrupt identity */
- if (priv->global.nr_ids < priv->ipi_id) {
- return VMM_EINVALID;
- }
+ /* Allocate interrupt identity for IPIs */
+ virq = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
+ if (virq < 0)
+ return virq;
+ priv->ipi_id = virq;
/* Reserve interrupt identity for IPI */
bitmap_set(priv->ids_used_bimap, priv->ipi_id, 1);
@@ -522,28 +523,28 @@ static int __init imsic_ipi_domain_init(struct imsic_priv *priv)
1, &imsic_ipi_domain_ops,
priv);
if (!priv->ipi_domain) {
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
return VMM_ENOMEM;
}
/* Pre-create IPI mappings */
- rc = vmm_host_irqdomain_create_mapping(priv->ipi_domain, 0);
- if (rc < 0) {
+ virq = vmm_host_irqdomain_create_mapping(priv->ipi_domain, 0);
+ if (virq < 0) {
vmm_lerror("imsic", "failed to create IPI mapping\n");
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
- return rc;
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
+ return virq;
}
skip_ipi:
/* Allocate interrupt identity for local enable/disable sync */
- rc = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
- if (rc < 0) {
+ virq = imsic_ids_alloc(priv, priv->global.nr_ids, get_count_order(1));
+ if (virq < 0) {
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
- return rc;
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
+ return virq;
}
- priv->ipi_lsync_id = rc;
+ priv->ipi_lsync_id = virq;
return VMM_OK;
}
@@ -552,7 +553,7 @@ static void __init imsic_ipi_domain_cleanup(struct imsic_priv *priv)
{
imsic_ids_free(priv, priv->ipi_lsync_id, get_count_order(1));
vmm_host_irqdomain_remove(priv->ipi_domain);
- bitmap_clear(priv->ids_used_bimap, priv->ipi_id, 1);
+ imsic_ids_free(priv, priv->ipi_id, get_count_order(1));
}
#else
static void imsic_ipi_enable(struct imsic_priv *priv)
@@ -914,9 +915,9 @@ static int __init imsic_init(struct vmm_devtree_node *node)
return VMM_EINVALID;
}
- /* Find interrupt indentity to be used for IPI */
- if (vmm_devtree_read_u32(node, "riscv,ipi-id", &priv->ipi_id))
- priv->ipi_id = 0;
+ /* Check if IPIs are slow */
+ priv->slow_ipi = vmm_devtree_getattr(node, "riscv,slow-ipi") ?
+ TRUE : FALSE;
/* Compute base address */
rc = vmm_devtree_regaddr(node, &global->base_addr, 0);
--
2.34.1
Anup Patel
Sep 29, 2022, 7:39:10 AM9/29/22
to xvisor...@googlegroups.com, Anup Patel
On Sun, Sep 25, 2022 at 11:26 PM Anup Patel <apa...@ventanamicro.com> wrote:
>
> This series brings the Xvisor AIA drivers in-sync with latest AIA spec
> and corresponding Linux AIA drivers.
>
> These patches can be found in riscv_aia_update_v1 branch at:
> https://github.com/avpatel/xvisor-next.git
>
> Anup Patel (4):
> RISC-V: Extend ISA string parsing for multi-letter extension names
> RISC-V: Remove riscv_aia_available feature flag
> DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
> DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
Applied this series to the xvisor-next repo.
>
> This series brings the Xvisor AIA drivers in-sync with latest AIA spec
> and corresponding Linux AIA drivers.
>
> These patches can be found in riscv_aia_update_v1 branch at:
> https://github.com/avpatel/xvisor-next.git
>
> Anup Patel (4):
> RISC-V: Extend ISA string parsing for multi-letter extension names
> RISC-V: Remove riscv_aia_available feature flag
> DRIVERS: irqchip/riscv-imsic: Remove [m|s|vs][set|clr]eipnum CSRs
> DRIVERS: irqchip/riscv-imsic: Use riscv,slow-ipi DT property
Thanks,
Anup
>
> arch/riscv/cpu/generic/cpu_init.c | 77 +++++++++---
> arch/riscv/cpu/generic/cpu_vcpu_helper.c | 6 +-
> arch/riscv/cpu/generic/include/cpu_hwcap.h | 31 +++--
> .../cpu/generic/include/riscv_encoding.h | 24 +---
> drivers/irqchip/irq-riscv-imsic.c | 116 +++++++++++++-----
> drivers/irqchip/irq-riscv-intc.c | 8 +-
> 6 files changed, 177 insertions(+), 85 deletions(-)
>
> --
> 2.34.1
>
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