Maglev：Adjuast condition bit code generation
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Yahan Lu
Sep 19, 2023, 10:23:57 PM9/19/23
to v8-dev
Hello everyone~
I want to port maglev to RISC-V, but there is no conditional bit code in RISC-V
So I need to remove the conditional bit code from the Maglev generic code.
I opened a CL (https://chromium-review.googlesource.com/c/v8/v8/+/4876814) to remove CompareInt32 and replace it with CompareInt32AndJumpIf.
If I can, I'll modify all cmp/assert in the maglev generic code.
I want to port maglev to RISC-V, but there is no conditional bit code in RISC-V
So I need to remove the conditional bit code from the Maglev generic code.
I opened a CL (https://chromium-review.googlesource.com/c/v8/v8/+/4876814) to remove CompareInt32 and replace it with CompareInt32AndJumpIf.
If I can, I'll modify all cmp/assert in the maglev generic code.
Yahan Lu
Sep 20, 2023, 1:24:08 AM9/20/23
to v8-dev
Do you have any opinion?
Leszek Swirski
Sep 20, 2023, 4:29:43 AM9/20/23
to v8-...@googlegroups.com
This seems like a reasonable thing to do yes, I'll review your CL.
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