loading wider vectors

[Sam Parker-Haynes]

Hi,

I'm looking a lot at shuffles, in turboshaft, and thinking about how we can generate de-interleaving loads. For AArch64 we have the LD1, LD2, LD3 and LD4 instructions which can load in a maximum of 4x128-bit values.

To simplify my life, I'm currently only considering LD2, which will load 2x128-bits, so I figure I the existing Simd256 operations would be good for this. But these are all currently predicated on V8_ENABLE_WASM_SIMD256_REVEC, do they have to be..?

I only want to support wide vectors for loads, using Simd256Extract128Lane to produce usable values for arithmetic, etc... but are there any parts of the pipeline that make assumptions when 'revec' is enabled that will make life hard?

And when trying to support LD3 (3x128-bit) and LD4 (4x128-bit), would this approach still scale?

Thanks,

Sam

[Matthias Liedtke]

Hi Sam,

As Wasm only supports Simd128, the Simd256 operations are part of an experimental (work-in-progress) implementation developed by Intel.

The progress is tracked here: https://crbug.com/42202660

The build flag is controlled here: https://source.chromium.org/chromium/chromium/src/+/main:v8/BUILD.gn;l=681;drc=9be9b0197a97a1f661c4cbf7b354c21ec3fcbe7f

When the build flag is set, it can be enabled with the flag --experimental-wasm-revectorize.

I don't think the current implementation tries to go further than 256 bit vector widths.

Cheers,

Matthias

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[Sam Parker-Haynes]

Hi Matthias,

Thanks for the links. I will try a build with the Simd256 type and operations enabled, but without the revec phase, and see how things go.

Cheers,

Sam