PDP11 speed

[Jonathan Harston]

I know the PDP11 didn't have what we'd recognise as a CPU clock, so

you can't really talk about a PDP11 "clocked at 2MHz". Individual instructions

are documented as taking specified times, and individual addressing modes

as taking additional times; the timing being essentially the result of the CPU

module placing signals on the bus and waiting for results from memory, with

hairy R/C networks regulating them.

However, the fastest* instruction timing in the 1979 PDP11 processor

handbook is the MOV/CLR/COM... group with Rn addressing mode at 1.96us.

Could I sorta then sorta call that 0.510MHz (1/1.96us). Other instruction

timings are not nice multiples of anything, we have 2.16us, 2.31us,

0.93us for (Rn), 2.17us for @(Rn)+, etc. But I want to have a base to

compare things, so I can time things and say "ah ha! this is running six

times faster than a 1979 PDP11, it's essentially a 3MHz system".

In a discussion on SlashDot in 2013 it is stated "the pdp11/45 ... a cycle

time of 300ns, so about 3.3MHz" so if we take "cycle time" as the shortest

time to get something from memory, which would be a single instruction

that doesn't access memory - eg MOV R0,R1 - then that's our "base" unit.

We then gloss over that instructions then appear to execute in non-integer-

multiples of cycles. :) ADD r0,r1 is 2.16us which is "1.1 cycles".

So, if I execute a loop decrementing a register from zero back to zero

again and it takes 0.2798437s, then it's functionally a 1979 0.5MHz system.

(*Ok, branch-not-taken is 1.76us.)

jgh

[Johnny Billquist]

I think you are a little mixed up.

There is a clock, as in something driven by a chrystal, on a PDP-11.
It's very much the same story as with any modern machine. Timing depends
on cache, addressing modes, memory speed, and all kind of stuff.

What you're describing do sound a lot like what the PDP-8 is doing, though.

But PDP-11 speed is both different in different models, but also
different implementations. So you can't just say a number for any
operation, addressing mode, or whatever. You'll need to be much more
specific on which machine you are talking about, and so on.

Johnny

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[Dwain Sims]

This brings up a question in my mind.

When I was in grad school in the early 80s we had a PDP 11/23 that the department ran Unix on and a couple of LSI-11 systems that primarily ran RT-11.  I never really thought about it at the time, but was there much difference in raw performance between the two?  I was not paying attention to that in that time frame (I was just happy to get access to any system.)  We certainly had more peripherals on the 11/23.  I recall that the only storage we had on the LSI-11 systems were 8 inch floppies.

Dwain

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[pbi...@gmail.com]

Read the thread https://retrocomputingforum.com/t/the-wide-ranging-performance-of-the-pdp-11/2615 and check out the "Computer Engineering" (and other) references.

[Johnny Billquist]

You got a link to a thread with some information on the performance of
different CPUs already.

But just to answer directly, yes, there is a significant difference
between the LSI-11 and the 11/23. But neither is close to the top of the
performance among PDP-11 models.

And to make another comment on clocks. As with most machines, talking
about the clock frequency is somewhat misleading, as you also need to
know how many clock cycles the CPU requires to do an instruction, which
differs between different architectures, but sometimes also between
different implementations of the same architecture. The PDP-11 is
definitely in that camp, so you need to look at a specific
implementation as well. But for the core clock, here are a couple of models:

11/70: 33.333 MHz
11/73: 15 MHz
11/8x: 18 MHz
11/9x: 18 MHz
11/2x: 26.667 MHz
11/03: 2.5 MHz (but this one is an RC network)

Nut, as mentioned, just talking about the frequency of clocks isn't
really that meaningful.

The classic example is the Z80 vs. 6502 comparisons. The Z80 (classic)
usually ran at 4 MHz, while the 6502 ran at 1 MHz.
However, the minimum number of cycles to do one instruction on the Z80
was 4, while on the 6502 it was 1, so in effect they were comparable for
doing a single instruction.

Johnny

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[Mark Matlock]

Dwain,

   Below is a comparison of bench marks that I measured and collected from PDP-11 and VAX systems that I have access to or own.

   I just recently acquired a PDP-11/03 and was able to compile the Dhrystone bench mark with RT-11 PDP-11C to compare it to the PDP-11/23 in my MINC-23. The Dhrystone bench mark has no floating point but PDP-11C does generate EIS instructions so I have not got a value yet for the PDP-11/05.

   On Floating point the 11/03 had optional FIS instructions and the 11/23 had FPP instructions either in microcode or as a separate board using bit slice chips as options. Below is microcode value for the 11/23. Also, below the 11/44 does not have the FPP option but used a DECUS FPP instruction trap software. The FIS instructions used the stack to pass floating point input and results and was supported by DEC’s threaded Fortran IV compiler, where DEC’s F77 compiler used the FPP instructions and compiled FPP instructions in-line. This gives the 11/23 a bigger advantage if you compare F77 on the 11/23 to Fortran IV on the 11/03. I’m in the process of evaluating that difference.

   Also, below the PDP-11/70 tests are from Jacob Ritorto’s PDP-11/70 that has some 3rd party performance options. It is the fastest 11/70 I tested hitting 1304 Dhrystones where other PDP-11/70s were more in the 1150 to 1200 range. Also, none of the big VAXes had FPP options since our accounting department didn’t used floating point calculations.

Best,

Mark

System          Sieve      Flops      Sieve   Float   Dhrys  Dhrystones

                                       VUPS    VUPS    VUPS     

PDP 11/03                                                 .13      200

PDP 11/23       .881628        10,178     .25     .05     .22      333

PDP 11/24                      11,500             .06

PDP 11/44       .568600        61,473     .39     .33

PDP 11/70       .204102       295,544    1.09    1.58     .87     1304

PDP 11/73       .319948        38,837     .69     .21     .56      833

PDP 11/83       .241563       359,416     .92    1.92     .77     1153

PDP 11/84       .236615       365,645     .94    1.95     .80     1200

M100-04         .218359       382,592    1.02    2.04     .83     1250

VAX 11/780      .222200       187,135    1.00    1.00    1.00     1500

uVAX II         .259100       144,829     .86     .77

VAX 8600        .059300     1,035,673    3.75    5.53

VAX 8700        .044920       885,201    4.95    4.73

VAX 6420        .032160     1,412,804    6.91    7.55   11.43    17141

VAX 6610        .007305     9,230,000   30.42   49.32   44.39    66578

VAX 3500        .084370       525,590    2.63    2.81    3.74     5612

MV3100 10e      .057030       766,470    3.90    4.10    5.89     8834

MV3100 30       .038906     1,132,743    5.71    6.05   10.65    15974

MV3100 80       .022187     1,987,578   10.01   10.62   15.15    22727

VS4000 90A      .007289     9,270,000   30.48   49.54   44.39    66578

Alpha 666Mhz    .000340   204,000,000  653.53    1090    1856  2783964  

[John Hudak]

There are some inaccuracies in your post.  The pdp11 cpu do in fact have clocks. As you point out, the instruction execution time, measured in clocks per instruction (CPI) varies with each instruction. The timing of a specific instruction will vary depending on what CPU is executing it. e.g. a mov mem-reg will be slower on a 11/04 versus an 11/70.  Point is, one needs to look at the processor handbook of the specific CPU to get the right instruction timing. This is due to implementation differences of the underlying hardware to do an instruction fetch, decode, execute.  So it is incorrect to compare cpu performance of two different PDP11s using clock frequency.  The base cpu instruction execution timing is determined without performance enhancements such as cache.  

The attempt to compare cpu performance using clocks of CPU, for example pdp11 to 68K, or 8086 etc. is also incorrect because the fundamental ISA is different.  The PDP11s are more closely aligned to the 8086 (even though it is a segmented architecture) than say the Sparc CPU, ARM or MIPS.  The latter are RISC type architectures designed to execute an instruction in one major clock cycle.  The execution sequence is generally fetch, decode, execute and writeback. 

One method to compare processor performance is to use benchmarking.  SPEC, SPECint, SPECfg (an others).  This approach introduces another set of variables  (e.g. compiler optimizations ) that can influence performance  comparisons between different machine architectures (generally CISC, RISC and specifically a PDP11/93 versus a RS6000. )  The benchmarks are more indicative of performance comparisons within a CPU family, e.g. pdp11/23 vs pdp11/73.   Digital created the VAX Unit of Performance (VUP) as a way to quantify relative performance across machines of the same architecture.  The VUP was essentially useless if used on a non VAX machine.  The rise is Dhrystones, Whetstones, and SPEC benchmarks allowed some better performance comparisons across different architectures.  Having said that, there are a number of ways to slant benchmarking numbers but that is a whole nother discussion.....

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[Jonathan Harston]

I'm not trying to compare PDP11 speed with other CPU speed, but PDP11 speed with

other PDP11 speed, mostly different versions of emulated PDP11s. If MOV R0,R0

executes in 1.96us on a 1979 PDP11/whatever and I can sorta call that "0.5MHz",

and from testing I find that MOV R0,R0 executes in 0.02us on EddiePDP emulator

running on a DT42 system, I can sorta call that "effectively a 20MHz PDP11". (Of

course, a full comparison would be timing a suite of various instructions to get a

spread across different instructions.)

I missed the 2022 thread on retrocomputing and StarDot, it contains useful information.

jgh

[Johnny Billquist]

Thing is, even different PDP-11 models will take different amount of
time for a MOV R0,R0, which is separate from clock speed.

Johnny

>    I just recently acquired a PDP-11/03 and was ableto compile

> <https://groups.google.com/d/msgid/pidp-11/02BA77A4-93C2-4BDA-
> B2E5-82A2D3A50084%40matlockfamily.com?
> utm_medium=email&utm_source=footer>.

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[Tomasz Rola]

On Wed, Jul 08, 2026 at 12:25:36AM -0700, pbi...@gmail.com wrote:
> Read the thread
> https://retrocomputingforum.com/t/the-wide-ranging-performance-of-the-pdp-11/2615
> and check out the "Computer Engineering" (and other) references.

I would also had a look at comments section in the following source:

https://web.archive.org/web/20150123191735if_/http://www.dunnington.u-net.com/public/dhrystone.c

It is just a synthetic benchmark, but on the other hand it offers some
numbers to chew upon.

The computers range from C-64 to various Cray models. And there are
some PDPs and Vaxen, too.

--
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Tomasz Rola

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** As the answer, master did "rm -rif" on the programmer's home **
** directory. And then the C programmer became enlightened... **
** **
** Tomasz Rola mailto:tomas...@bigfoot.com **

[terri-...@glaver.org]

On Wednesday, July 8, 2026 at 7:05:34 PM UTC-4 b...@softjar.se wrote:

Thing is, even different PDP-11 models will take different amount of
time for a MOV R0,R0, which is separate from clock speed.

Exactly. And "benchmarks" for a particular PDP-11 model tend to neglect things like memory type (some models could have core or either of two types of semiconductor memory), the 11/70 talked to memory 32 bits at a time, later PDP-11s supported PMI memory, and so on. Add on memory interleave (where appropriate) and speeds can change dramatically as well.

Then you get into optional instruction sets (EIS / FIS / DIS / FPP / CIS) which can help certain benchmarks.

Not to mention operating system overhead, other tasks running, etc.

Clocks on PDP-11s were 'interesting'. As noted in the linked 2022 article, the J-11 used an external crystal running at 4x the actual "system clock" rate. So an "18MHz" J11 was actually a 4.5MHz part. The Intel 8080 did something similar, as did many other microprocessors that existed during the PDP-11's lifespan.

The PDP-11/70 used the M8139, a quad-wide board, to generate most of the processor timing. It is an incredibly complex mixed-signal board notoriously difficult to work on (it won't run reliably on an extender). And the 11/70 is partially synchronous and partially asynchronous.

[pbi...@gmail.com]

What is "DIS"?

EIS = Extended Instruction Set

FIS = Floating Instruction Set

FPP = Floating Point Processor (believe that this varies a bit depending on model/option)

CIS = Commercial Instruction Set

[Jon Callas]

> On Jul 10, 2026, at 23:18, pbi...@gmail.com <pbi...@gmail.com> wrote:
>
> What is "DIS"?
>

DIBOL Instruction Set. It was a "commercial" set with packed decimal, string instructions, and some others.

Jon

[Johnny Billquist]

I've only seen one or two references to that one. And it seemed to have
been a very short lived thing that was only ever available for the
LSI11. And no version of Dibol I've seen even mentions it.
(And hoping I didn't get any details wrong here...)

Johnny

[Anton Lavrentiev]

https://gunkies.org/wiki/KEV11-C_Commercial_Instruction_Set

Looks like just yet another name for what's better known as CIS

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[Johnny Billquist]

"A subset of CIS".

Johnny

On 2026-07-11 15:48, Anton Lavrentiev wrote:
> https://gunkies.org/wiki/KEV11-C_Commercial_Instruction_Set <https://
> gunkies.org/wiki/KEV11-C_Commercial_Instruction_Set>

>
> Looks like just yet another name for what's better known as CIS
>
> On Sat, Jul 11, 2026, 9:11 AM Johnny Billquist <b...@softjar.se
> <mailto:b...@softjar.se>> wrote:
>
> On 2026-07-11 09:01, Jon Callas wrote:
> >
> >
> >> On Jul 10, 2026, at 23:18, pbi...@gmail.com

> <mailto:pbi...@gmail.com> <pbi...@gmail.com

> <mailto:pbi...@gmail.com>> wrote:
> >>
> >> What is "DIS"?
> >>
> >
> > DIBOL Instruction Set. It was a "commercial" set with packed
> decimal, string instructions, and some others.
>
> I've only seen one or two references to that one. And it seemed to have
> been a very short lived thing that was only ever available for the
> LSI11. And no version of Dibol I've seen even mentions it.
> (And hoping I didn't get any details wrong here...)
>
>    Johnny
>
> --
> Johnny Billquist                  || "I'm on a bus
>                                    ||  on a psychedelic trip

> email: b...@softjar.se <mailto:b...@softjar.se>             ||

> Reading murder books
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[Johnny Billquist]

By the way, the versions of Dibol I've seen (or have) don't even use CIS.
The only product that can generate code for CIS that I've ever seen is
Cobol.

Johnny

[terri-...@glaver.org]

On Saturday, July 11, 2026 at 9:11:55 AM UTC-4 b...@softjar.se wrote:

I've only seen one or two references to that one. And it seemed to have
been a very short lived thing that was only ever available for the
LSI11. And no version of Dibol I've seen even mentions it.
(And hoping I didn't get any details wrong here...) 

 
DEC tried selling a multi-user DIBOL system based on the LSI-11. It was one of those packaged "DECdatasystem" or similar systems. It obviously didn't have enough "oomph"*, even with the DIS option, so DEC transitioned the product to be 11/23 based as soon as the F11 CPU was available.

John Wilson has an LSI-11 DIS chip, I believe. His E11 is a diagnostics-passing PDP-11 emulator that runs on everything from bare x86 metal to Windows / Linux.

* Alpha Micro used the WD1600 (the LSI-11 chipset with different microcode**) to build multi-user systems that sort of looked like RSTS. 16 terminals on LSI-11 class hardware.

** I know of four, possibly five microcode variants for the WD1600:
1) The LSI-11
2) Native WD1600
3) Alpha Micro
4) Pascal MicroEngine
5) A custom one for Western Electric used in early high end stat muxes
Alpha Micro may have used the native instruction set, I'm not sure.

[Jon Callas]

> On Jul 11, 2026, at 06:11, Johnny Billquist <b...@softjar.se> wrote:
>
> On 2026-07-11 09:01, Jon Callas wrote:
>>> On Jul 10, 2026, at 23:18, pbi...@gmail.com <pbi...@gmail.com> wrote:
>>>
>>> What is "DIS"?
>>>
>> DIBOL Instruction Set. It was a "commercial" set with packed decimal, string instructions, and some others.
>
> I've only seen one or two references to that one. And it seemed to have been a very short lived thing that was only ever available for the LSI11. And no version of Dibol I've seen even mentions it.
> (And hoping I didn't get any details wrong here...)

I'm primarily a Vax guy, myself, but rummaging around in things tells me that CIS was only supported on the 11/44, and the F-11 CPUs (11/23, 23+, 11/24), and this was for the 11/03, and was a subset of DIS for the 11/03.

https://gunkies.org/wiki/KEV11-C_Commercial_Instruction_Set
https://gunkies.org/wiki/PDP-11_Commercial_Instruction_Set
https://gunkies.org/wiki/KDF11_CPUs

Jon

[Clem Cole]

below

On Sat, Jul 11, 2026 at 11:42 AM terri-...@glaver.org <terri-...@glaver.org> wrote:

...

** I know of four, possibly five microcode variants for the WD1600:
1) The LSI-11
2) Native WD1600
3) Alpha Micro
4) Pascal MicroEngine
5) A custom one for Western Electric used in early high end stat muxes
Alpha Micro may have used the native instruction set, I'm not sure.

I believe a couple of the Aerospace/DoD folks in Irvine/S. CA, folks like Hughes, Grumman, TRW et al, had projects that used the WD MCP-1600 family.  One of my friends had a summer job with one of them (TRW, I think, but I've long ago forgotten) and did microcoding with that chip for them.  It is possible they were using the WD 9000 [http://pascal.hansotten.com/ucsd-p-system/western-digital-micro-engine/], which was the HW base for the Pascal engine, but with different microcode. I also have no idea what became of those projects.

Also, althought I personally didn't do much with it, as it was just coming up/getting stable around the time I graduated, my brothers and sisters at CMU who were building CM* for the compute nodes used DEC LSI-11 boards (stock quad-height M7264 — KD11-F with KEV11-A/EIS processors).  They used both the stock WD MCP-1600 (original DEC-defined 11/5 emulation/written by WD) ucode and they built a WSC feature that was exploited for certain functions.  Although I may be remembering incorrectly, I don't think all nodes had WSC.  But adding WSC allowed them to replace portions of the standard DEC LSI-11 microcode with custom microprograms to accelerate operating-system primitives (e.g., faster context switching for StarOS and Medusa).  I also don't remember if they added csv/cret instructions like the 11/40Es; but that was a popular hack at CMU in those days if your processor could support it, and with a limited 64K address size, the smaller binary alone made it useful [Note the "Pmap" processor in the Kmaps was AMD 2900 family, however].   ISTR the ucode tools were homegrown, ran on the PDP-10s, and used the same toolset as the 11/40E systems in C.mmp and the UNIX systems IUS and SUS (which had csv/cret - I used to program those systems and a couple of other 11/40Es, and used the tools for them).

[tsyb...@gmail.com]

And another one

https://forum.vcfed.org/index.php?threads/pdp-11-%CF%80-benchmark.56998/

[Jacob Ritorto]

On Wed, Jul 8, 2026 at 07:10 Mark Matlock <ma...@matlockfamily.com> wrote:

  Also, below the PDP-11/70 tests are from Jacob Ritorto’s PDP-11/70 that has some 3rd party performance options. It is the fastest 11/70 I tested hitting 1304 Dhrystones where other PDP-11/70s were more in the 1150 to 1200 range. Also, none of the big VAXes had FPP options since our accounting department didn’t used floating point calculations.

Those “third party performance options” likely responsible for the high ratings are the Setasi PEP-70 and HyperCache. Tom Uban should be noted here as the prior curator of this system — seems it’s a particularly wonderful one and wonderfully preserved due to Tom’s diligence in care.  Thanks again, Tom!

—Jake