Contact Oscar for parts

[Laurent Dizy]

Hi

i need to order parts, i have sent some mail to Oscar, but maybe at the wrong adresse because, i do not have any answer.....

How can i contact him ?

regards

[Glenn Babecki]

In the early days I believe Oscar was using a Hotmail account when he was running things as a one-man operation.  Now I think the preferred contact for orders and questions is via the operations email address:  os...@ceds.dev

That said, Oscar has participated in forum threads with the email address:  vermeul...@gmail.com.

Hope this helps and you can contact him.

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[Peter Ekstrom]

I understand he has a lot going on at times, so be patient and give him some time. I'm sure he will respond.

He is also active in this group so he will see this post as well.

-Peter

--

[oscarv]

Hi,

Apologies if I missed a parts request! I'm having these recurring Brain Fog episodes, apparently nothing serious but very annoying. I just was knocked off-line by it for a good 10 days.

Yes, partly in response to this we've - well, not professionalised(*), but improved things. Jose Leon is taking over a lot of support. So just email him at j.l...@ceds.dev, and we'll send you the parts! Free if it is my fault, at cost if you deem it yours, just let us know :-)

Kind regards,

Oscar.

(*)Professionalised? Not quite, the son of my friend Otto sends the parts out of Canada. But we do it with tracking number etc, so quite professional :-)

[Edward Tottenham]

Hi all,

I'm (very slowly) building an FPGA version of a PDP 11/70 running using the actual Microcode from the PDP 11/70.

As verification, I'm using the CPU Diagnostics from here
https://bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0095_CZKDJB0_KDJ11.pdf

I'm having problems with the ASHC instruction tests, and as far as I can make out the diagnostic code is just plain wrong.

The code, effectively does:

MOV
6052 026432 177731 .word 177731 ; Source WAS 177725, but that makes no sense
6053 026434 177777 .word 177777 ; Destination Word 1
6054 026436 177400 .word 177400 ; Destination Word 2
6055 026440 000007 .word 7 ; Expected PSW
6056 026442 000000 .word 000000 ; Result word 1
6057 026444 000000 .word 000000 ; Result word 2

[Edward Tottenham]

Hi all,

Sorry, my previous version of this email got sent too soon, ignore that one.

I'm (very slowly) building an FPGA version of a PDP 11/70 running using the actual Microcode from the PDP 11/70.

As verification, I'm using the CPU Diagnostics from here
https://bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0095_CZKDJB0_KDJ11.pdf

I'm having problems with the ASHC instruction tests, and as far as I can make out the diagnostic code is just plain wrong.

I'm hoping that someone here can tell me that I'm either insane (with the reason why) or that I'm correct (in which case how did the diagnostic ever work?).
The code, effectively does:

MOV #177725, R4 ; Shift count (only 6 bits used)

MOV #177777,R2 ; High 16 bits of value
MOV #177400,R3 ; Lo 16 bits of value

SCC
ASH R4,R2 ; Shift the two registers

CMP R2,#0 ; Result should be zero
BNE Error
CMP R3,#0 ; Result should be zero
BNE Error

So, it is expecting a zero result.

The ASHC instruction will only look at the bottom 6 bits or R4, so 25 (octal) as the shift count. It will shift it 21 (decimal) bits to the left. No matter how I look at it, this is going to return a result of

R2 = 160000
R3 = 000000

i.e. three bits left in the highest bits. In order to end up with zero in both registers, the shift count needs to be 24. or 30 octal doesn't it.

Can anyone enlighten me

All the best
Ed Tottenham

[Folkert van Heusden]

Hi,

Verification is a very interesting toppic.

I've written a PDP 11/70 emulator as well and the lack of convenient tools made that problematic.

Something I should've done earlier but done a few months ago is instrumenting simh to execute instructions and then for each variant of such an instructing output the random initialization of each instruction and the resulting outcome. I've put that in json-files (several gigabytes in size) that I then read and process with my own emulator. I could've just duplicated the code of simh but what's the fun of that...?

Ideally the cpu of a real pdp is taken out of its system and breadboarded to do a clean production of the instructions, their outcomes and maybe even execution time.

Note that this procedure is not new: emulator developers of the 80x86 series, the 6502 etc etc have done this as well (including pulling out the processor and doing the breadboard trick).

regards

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[Johnny Billquist]

Uh... You missed that the shift value is signed...? This is a negative
shift... Meaning a shift to the right.

Johnny

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|| on a psychedelic trip
email: b...@softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol

[Anton Lavrentiev]

> This is a negative shift...

How come? The sign bit is bit <5> (counting from 0), which is in
octal 25 is 0, meaning the value is positive 21 (decimal).
47 would have been a negative 21 (decimal).

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[Johnny Billquist]

D'oh! Sorry, my mistake.
You are right, the signedness should be within those 6 bits, this would
indeed be a left shift.

By the way, I also hope your "ASH" actually was an "ASHC" in the code
you typed in below.

But I agree that with those assumptions, I also can't see how it would
end up with R2/R3 being zero. I agree that R2 would end up with 160000.

Johnny

[Anton Lavrentiev]

> 47 would have been a negative 21 (decimal).

Ugh, 53 obviously, not 47.

[Johnny Billquist]

On 2025-05-09 18:32, Anton Lavrentiev wrote:
>> This is a negative shift...
>
> How come? The sign bit is bit <5> (counting from 0), which is in
> octal 25 is 0, meaning the value is positive 21 (decimal).
> 47 would have been a negative 21 (decimal).

/me idiot and not looking enough before responding.

Johnny

>
> On Fri, May 9, 2025 at 12:26 PM Johnny Billquist <b...@softjar.se> wrote:
>>
>> Uh... You missed that the shift value is signed...? This is a negative
>> shift... Meaning a shift to the right.
>>
>> Johnny
>>
>> On 2025-05-09 18:08, Edward Tottenham wrote:
>>> Hi all,
>>>
>>> Sorry, my previous version of this email got sent too soon, ignore that one.
>>>
>>> I'm (very slowly) building an FPGA version of a PDP 11/70 running using the actual Microcode from the PDP 11/70.
>>>
>>> As verification, I'm using the CPU Diagnostics from here
>>> https://bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0095_CZKDJB0_KDJ11.pdf
>>>
>>> I'm having problems with the ASHC instruction tests, and as far as I can make out the diagnostic code is just plain wrong.
>>>

>>> I'm hoping that someone here can tell me that I'm either insane (withthe reason why) or that I'm correct (in which case how did the diagnostic ever work?).

>>> The code, effectively does:
>>>
>>> MOV #177725, R4 ; Shift count (only 6 bits used)
>>>
>>> MOV #177777,R2 ; High 16 bits of value
>>> MOV #177400,R3 ; Lo 16 bits of value
>>>
>>> SCC
>>> ASH R4,R2 ; Shift the two registers
>>>
>>> CMP R2,#0 ; Result should be zero
>>> BNE Error
>>> CMP R3,#0 ; Result should be zero
>>> BNE Error
>>>
>>> So, it is expecting a zero result.
>>>

>>> The ASHC instruction will only look at the bottom 6 bits or R4, so 25(octal) as the shift count. It will shift it 21 (decimal) bits to the left. No matter how I look at it, this is going to return a result of

>>>
>>> R2 = 160000
>>> R3 = 000000
>>>
>>> i.e. three bits left in the highest bits. In order to end up with zero in both registers, the shift count needs to be 24. or 30 octal doesn't it.
>>>
>>> Can anyone enlighten me
>>>
>>> All the best
>>> Ed Tottenham
>>>
>>
>> --
>> Johnny Billquist || "I'm on a bus
>> || on a psychedelic trip
>> email: b...@softjar.se || Reading murder books
>> pdp is alive! || tryin' to stay hip" - B. Idol
>>
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>

[Edward Tottenham]

Looking at the Microcode, it only actually loads the bottom 6 bits into the SC register which is used for counting. So, even though R4 is a negative number, the lower six bits are actually a positive number. The sign bit is, effectively bit 5.

The manual says that the range of the shift is -32 to +31 (40 to 37 in octal) 177725 would be -43 decimal, so out of range,

Ed

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[Edward Tottenham]

Yes, it should have been ASHC.

Ed

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[Johnny Billquist]

One thing comes to mind. Are you sure the code isn't modifying the
constant loaded into R4 at some other place at runtime? Self-modifying
code was not unheard of in the past...

Another possibility would be that the program flow gets in after the
loading of R4 to verify correctness. Possibly even expecting it to fail
at a first run, and work at a second?

Johnny

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>

[Anton Lavrentiev]

Believe it or not, there are bugs even in the diagnostic packages ;-)
Depending on if they were ever actually run in the field. As some
obviously never had been.

> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/74461006.1333016.1746808615238%40email.ionos.co.uk.

[Johnny Billquist]

What I can also say is that on a J11, with that exact code, you will get
R2=160000, as expected. :-)

Johnny

[Johnny Billquist]

A possibility.

Which diagnostic is this?

Johnny

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[Edward Tottenham]

Interesting, so how on earth did DEC engineers get that test to run, or is that listing not up to date.

The test is the one starting at the label 9$: in TST215 on page SEQ 0416 of the document at:

https://bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0095_CZKDJB0_KDJ11.pdf

Ed

> On 09/05/2025 17:33 BST Johnny Billquist <b...@softjar.se> wrote:
>
>

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[Johnny Billquist]

Thanks. I just realized you posted the link before as well.

Since I've run lots of diagnostics on real 11/70 machines, I figured I
could possibly verify if I've run that one...

I'll try to dig through my memory a bit and come back on that one. I'll
also check your link to read the code...

Johnny

On 2025-05-09 18:43, Edward Tottenham wrote:
> Interesting, so how on earth did DEC engineers get that test to run, oris that listing not up to date.

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>

[Johnny Billquist]

Oh! First of all, this is not diagnostics intended for the 11/70. This
is for the KDJ11-A CPU.

Second, the diagnostics are actually testing for a buggy J11.

See
http://www.bitsavers.org/pdf/dec/pdp11/xxdp/PDP11_DiagnosticHandbook_1988.pdf,
page 91. The "current" version of that diagnostic is ZKDJB2, which
address a bug in the J11 related to ASH and ASHC... :-)

(The two last letters of a diagnostic name is a version number. You're
looking at B0, while the correct version would be B2).

Johnny

On 2025-05-09 18:43, Edward Tottenham wrote:

> Interesting, so how on earth did DEC engineers get that test to run, oris that listing not up to date.

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>

[Edward Tottenham]

Unless I've copied it wrongly, there's a copy of just that test here:

https://www.dropbox.com/scl/fi/6cgwe0hi0068zld0it1rq/ASHC_Tests.mac?rlkey=lxs07sssyg90auzmbjrpn1fcg&st=ac84sv9b&dl=0

It would have to run as a priveliged task on RSX since it accesses the PSW directly using @#177776.

I'd be very grateful if you could check it. My assumption was that the code had to be correct, so I spent a few days chasing my tail with a logic analyser trying to find why it failed. I was a bit slow at realising that the shift count looked wrong.

Ed

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[Edward Tottenham]

Thanks for the bad news :(

Any idea where there might be a listing of the correct code?

My processor is very limited at the moment, so I can't read from disks yet.

All the best
Ed

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[Anton Lavrentiev]

You've copied 174000 as 177400, so you got 3 additional "1" bits...
Please re-check your source with the listing (line 7919)

> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/256012235.1334683.1746809732171%40email.ionos.co.uk.

[Johnny Billquist]

If you are working on an 11/70 implementation you shouldn't even care
about that test program. It's for a different implementation of the PDP-11.

Unfortunately it don't look like the 11/70 diagnostics sources have been
scanned (I don't know if anyone even have copies).
But the actual binaries as such do exist.

Johnny

>> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/1e35eb32-1c81-4aa1-8037-a141db97c885%40softjar.se.

[Edward Tottenham]

I don't believe it, you're right. And I've started at that code 100 times.

Thanks very much, you've stopped me from going totally insane.

Cheers
Ed

[Edward Tottenham]

OK, I'll just have to try to get sufficient working to be able to boot the diagnostics off disk.

I'm hoping an RK05 version exists, since that is the only disk I have got working (for reading anyway) so far.

Ed

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[Johnny Billquist]

Ooo. Nice catch. I never even went and looked, since I saw the note on
changes to the diagnostics with notes saying that even version B1 will
fail on a revised J11 on the ASH/ASHC tests...

So I still think revision B0 of that test program is testing things
wrong on ASH/ASHC compared to what actually should happen. But maybe in
some more subtle way then...?

Anyway, since this is tests for a different implementation to start
with, I'm not sure if this is the best way to continue...

Johnny

On 2025-05-09 18:59, Anton Lavrentiev wrote:
> You've copied 174000 as 177400, so you got 3 additional "1" bits...
> Please re-check your source with the listing (line 7919)
>
> On Fri, May 9, 2025 at 12:55 PM Edward Tottenham <edw...@tottenham.name> wrote:
>>
>> Unless I've copied it wrongly, there's a copy of just that test here:
>>
>> https://www.dropbox.com/scl/fi/6cgwe0hi0068zld0it1rq/ASHC_Tests.mac?rlkey=lxs07sssyg90auzmbjrpn1fcg&st=ac84sv9b&dl=0
>>

>> It would have to run as a priveliged task on RSX since it accesses thePSW directly using @#177776.
>>
>> I'd be very grateful if you could check it. My assumption was that thecode had to be correct, so I spent a few days chasing my tail with a logic analyser trying to find why it failed. I was a bit slow at realising that the shift count looked wrong.

>>
>> Ed
>>
>>> On 09/05/2025 17:46 BST Johnny Billquist <b...@softjar.se> wrote:
>>>
>>>
>>> Thanks. I just realized you posted the link before as well.
>>>
>>> Since I've run lots of diagnostics on real 11/70 machines, I figured I
>>> could possibly verify if I've run that one...
>>>
>>> I'll try to dig through my memory a bit and come back on that one. I'll
>>> also check your link to read the code...
>>>
>>> Johnny
>>>
>>> On 2025-05-09 18:43, Edward Tottenham wrote:

>>>> Interesting, so how on earth did DEC engineers get that test to run,oris that listing not up to date.

>> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/256012235.1334683.1746809732171%40email.ionos.co.uk.

[Johnny Billquist]

Paper tape, baby... Which can mean getting it all via the serial port. :-)

Although, the exercise of getting that setup and working is not
something I have any experience with. But the diagnostics binaries are
(I believe) in BIN format, for which there is a boot loader to be found
somewhere...

Johnny

>>>>> The test is the one starting at the label 9$: in TST215 on page SEQ0416 of the document at:

>>>>>> You received this message because you are subscribed to the GoogleGroups "[PiDP-11]" group.

>>>>>> To unsubscribe from this group and stop receiving emails from it, sendan email to pidp-11+u...@googlegroups.com.
>>>>>> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/d97cb0a6-faa7-40fc-87f6-b1ac6dba7867%40softjar.se.
>>>>>
>>>>
>>>> --
>>>> Johnny Billquist || "I'm on a bus
>>>> || on a psychedelic trip
>>>> email: b...@softjar.se || Reading murder books
>>>> pdp is alive! || tryin' to stay hip" - B. Idol
>>>>
>>>> --
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>>
>> --
>> Johnny Billquist || "I'm on a bus
>> || on a psychedelic trip
>> email: b...@softjar.se || Reading murder books
>> pdp is alive! || tryin' to stay hip" - B. Idol
>>
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[Johnny Billquist]

And just for the record, here is my small snippet of code to check the
results of the specific test:

.TITLE TSTASH
.LIBRARY /LB:[1,1]BQTMAC/

.MCALL .MSG, EXIT$S

.PSECT CODE,I,RO
START: .MSG <"Hello world">
MOV #177725,R4
MOV #177777,R2
MOV #177400,R3
ASHC R4,R2
.MSG <"%P,%P,%P">,<R2,R3,R4>
EXIT$S

.END START

for RSX. Running, it gives:

Hello world
160000,000000,177725


Johnny

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[Anton Lavrentiev]

While it might be true that it's for a different CPU, (if the listing
is bug free) I don't think that there are going to be any
discrepancies in these basic arithmetic tests across various PDP-11
CPU models.

[Johnny Billquist]

Many diagnostics are testing undocumented, undefined behaviors.
The basic instructions should of course work the same in the defined
domains. However, when it comes to less defined situations, things
become "funnier".

Johnny

On 2025-05-09 19:23, Anton Lavrentiev wrote:

>>>>>>>>> I'm having problems with the ASHC instruction tests, and as faras I

>>>>>>>>> can make out the diagnostic code is just plain wrong.
>>>>>>>>>
>>>>>>>>> I'm hoping that someone here can tell me that I'm either insane(with
>>>>>>>>> the reason why) or that I'm correct (in which case how did the
>>>>>>>>> diagnostic ever work?).
>>>>>>>>> The code, effectively does:
>>>>>>>>>
>>>>>>>>> MOV #177725, R4 ; Shift count (only 6 bits used)
>>>>>>>>>
>>>>>>>>> MOV #177777,R2 ; High 16 bits of value
>>>>>>>>> MOV #177400,R3 ; Lo 16 bits of value
>>>>>>>>>
>>>>>>>>> SCC
>>>>>>>>> ASH R4,R2 ; Shift the two registers
>>>>>>>>>
>>>>>>>>> CMP R2,#0 ; Result should bezero
>>>>>>>>> BNE Error
>>>>>>>>> CMP R3,#0 ; Result should bezero
>>>>>>>>> BNE Error
>>>>>>>>>
>>>>>>>>> So, it is expecting a zero result.
>>>>>>>>>

>>>>>>>>> The ASHC instruction will only look at the bottom 6 bits or R4,so 25

>>>>>>>>> (octal) as the shift count. It will shift it 21 (decimal) bits tothe
>>>>>>>>> left. No matter how I look at it, this is going to return a result of
>>>>>>>>>
>>>>>>>>> R2 = 160000
>>>>>>>>> R3 = 000000
>>>>>>>>>
>>>>>>>>> i.e. three bits left in the highest bits. In order to end up withzero
>>>>>>>>> in both registers, the shift count needs to be 24. or 30 octal doesn't
>>>>>>>>> it.
>>>>>>>>>
>>>>>>>>> Can anyone enlighten me
>>>>>>>>>
>>>>>>>>> All the best
>>>>>>>>> Ed Tottenham
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Johnny Billquist || "I'm on a bus
>>>>>>> || on a psychedelic trip
>>>>>>> email: b...@softjar.se || Reading murder books
>>>>>>> pdp is alive! || tryin' to stay hip" - B. Idol
>>>>>>>
>>>>>>> --
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>>>>>>> To unsubscribe from this group and stop receiving emails from it,sendan email to pidp-11+u...@googlegroups.com.

>>>>>>> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/d97cb0a6-faa7-40fc-87f6-b1ac6dba7867%40softjar.se.
>>>>>>
>>>>>
>>>>> --
>>>>> Johnny Billquist || "I'm on a bus
>>>>> || on a psychedelic trip
>>>>> email: b...@softjar.se || Reading murder books
>>>>> pdp is alive! || tryin' to stay hip" - B. Idol
>>>>>
>>>>> --
>>>>> You received this message because you are subscribed to the Google Groups "[PiDP-11]" group.
>>>>> To unsubscribe from this group and stop receiving emails from it, send an email to pidp-11+u...@googlegroups.com.
>>>>> To view this discussion visit https://groups.google.com/d/msgid/pidp-11/44d32cd9-c3c3-4469-9e4f-18981202e4e3%40softjar.se.
>>>>
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>>
>> --
>> Johnny Billquist || "I'm on a bus
>> || on a psychedelic trip
>> email: b...@softjar.se || Reading murder books
>> pdp is alive! || tryin' to stay hip" - B. Idol
>>

[Johnny Billquist]

And there are documented differences in behavior between the KB11 and J11.

Johnny

[Anton Lavrentiev]

> And there are documented differences in behavior between the KB11 and J11.

Right, and I don't disagree with that. But they would be in much
trickier things than just plain ASH(C) instructions (or other basic
integer arithmetic operations, for that matter).

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[Johnny Billquist]

On 2025-05-09 19:34, Anton Lavrentiev wrote:
>> And there are documented differences in behavior between the KB11 and J11.
>

> Right, and I don't disagree with that. But they would be in much
> trickier things than just plain ASH(C) instructions (or other basic
> integer arithmetic operations, for that matter).

There are lots of things, even excluding the fact that the J11 CPU have
instructions that don't exist in the KB11.

But a simple thing like MOV R0,(R0)+ will produce different results on a
KB11 and a J11.

Johnny

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[Anton Lavrentiev]

You're missing my point entirely. Yes, that would produce a different
outcome, but I was talking about _arithmetic_ tests which do not
involve any such "trickeries", but rather simple computations.
For example, that ASHC test from the listing is not using anything
special that would come out differently across different CPU models.

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[Johnny Billquist]

And I was pointing out that I think it's a bad idea to use diagnostics
tests designed for the J11 if you want to implement a KB11. :-)

And the fact that they are checking the results of the PSW (luckily
enough both of these CPUs can at least read the PSW via an address, and
the J11 tests is using that), means that they are looking at possible
effects of instructions that might be undefined behavior as well.

Johnny

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[Johnny Billquist]

Example of an undefined thing with ASHC, just to give you a possible
example. And to tell the truth, I don't know how either processor works
on this, and documentation does not tell. They might behave the same,
but then again, maybe not?

ASHC defines that the carry bit will high order bit when shifted left,
and the low order bit when shifted right. But what will the carry get if
the shift count is zero?

Johnny

>>> pidp-11/fcf4d713-7971-4936-a235-b519ac3490f9%40softjar.se.

[Anton Lavrentiev]

The behavior with 0 bit shifts is explicitly documented that the
operation sets up all condition bits properly, meaning that "C" is
always 0 in this case.

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[Anton Lavrentiev]

Well, may be not... I re-read the doc that it is vague about "C".
I'd say it may be left unchanged, or zeroed, since nothing was shifted
out into it.
But I agree it's a gray area

[Johnny Billquist]

On 2025-05-09 20:03, Anton Lavrentiev wrote:
> The behavior with 0 bit shifts is explicitly documented that the
> operation sets up all condition bits properly, meaning that "C" is
> always 0 in this case.

The test verify that this is the case, yes. It's not documented in any
processor handbook. And it does not mean other processors do the same.

And just to point out, before executing the ASHC, the C bit is set to 1,
so in this case ASHC cleared the C bit.

Johnny

[Thalia Archibald]

Hi everyone,

What documents are you referencing for simulating the PDP-11/70 microcode?

I became interested in writing a microcode simulator after writing a bunch of C
and assembly code on Unix v5, but having no way to accurately measure its
performance close to the real hardware. As far as I know, SIMH doesn’t simulate
instruction timings. It seems difficult to simulate timings for CPU
instructions, as they vary by addressing mode and other minute details, and
complex instructions like from the Commercial Instruction Set have many
underlying algorithms that could differ in an emulation. So, I was led to
wanting to build an accurate microcode simulator, as I assume that
microinstruction timings compose better than CPU instructions.

I’ve had difficulty finding good documentation on microcode, though. There’s
such a mass of documents on bitsavers that I haven’t reviewed and the
multi-hundred-page manuals I have reviewed have been time-consuming. Is there an
annotated index of PDP-11 documents on bitsavers? I’m particularly interested in
microcode documentation for the PDP-11/70, matching my PiDP, and the PDP-11/44,
as it supports the Commercial Instruction Set.

I found Jörg Hoppe’s PDP11GUI which lets you step through the PDP-11/44
microinstructions of the current instruction:

https://www.retrocmp.com/pdp-11/pdp11gui/1144-mcode
https://github.com/j-hoppe/PDP11GUI/blob/master/Pdp11gui/Pdp1144MicroCodeU.pas

It uses OCR'd microcode listings from the PDP-11/44 Processor Maintenance
Supplementary Listings:

https://bitsavers.org/pdf/dec/pdp11/1144/EY-C3012-RB-001_Microcode_Listing_Apr81.pdf
https://bitsavers.org/pdf/dec/pdp11/1144/EY-C3012-RB-001_Microcode_Listing_Apr81.txt

I haven’t yet determined whether those microcode listings are sufficient to
reconstruct the microcode or I’d need something additional.

Any pointers would be welcome.

Thanks,
Thalia Archibald

> On May 9, 2025, at 09:08, Edward Tottenham <edw...@tottenham.name> wrote:
>
> Hi all,
>
> Sorry, my previous version of this email got sent too soon, ignore that one.
>
> I'm (very slowly) building an FPGA version of a PDP 11/70 running using the actual Microcode from the PDP 11/70.
>
> As verification, I'm using the CPU Diagnostics from here
> https://bitsavers.org/pdf/dec/pdp11/xxdp/fiche_200dpi/0095_CZKDJB0_KDJ11.pdf
>

> I'm having problems with the ASHC instruction tests, and as far as I can make out the diagnostic code is just plain wrong.
>
> I'm hoping that someone here can tell me that I'm either insane (with the reason why) or that I'm correct (in which case how did the diagnostic ever work?).

> The code, effectively does:
>
> MOV #177725, R4 ; Shift count (only 6 bits used)
>
> MOV #177777,R2 ; High 16 bits of value
> MOV #177400,R3 ; Lo 16 bits of value
>
> SCC
> ASH R4,R2 ; Shift the two registers
>
> CMP R2,#0 ; Result should be zero
> BNE Error
> CMP R3,#0 ; Result should be zero
> BNE Error
>
> So, it is expecting a zero result.
>

> The ASHC instruction will only look at the bottom 6 bits or R4, so 25 (octal) as the shift count. It will shift it 21 (decimal) bits to the left. No matter how I look at it, this is going to return a result of

>
> R2 = 160000
> R3 = 000000
>

> i.e. three bits left in the highest bits. In order to end up with zero in both registers, the shift count needs to be 24. or 30 octal doesn't it.

>
> Can anyone enlighten me
>
> All the best
> Ed Tottenham
>
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[terry-...@glaver.org]

On Friday, May 9, 2025 at 11:32:42 PM UTC-4 Thalia Archibald wrote:

What documents are you referencing for simulating the PDP-11/70 microcode?

I’ve had difficulty finding good documentation on microcode, though. There’s
such a mass of documents on bitsavers that I haven’t reviewed and the
multi-hundred-page manuals I have reviewed have been time-consuming. Is there an
annotated index of PDP-11 documents on bitsavers? I’m particularly interested in
microcode documentation for the PDP-11/70, matching my PiDP, and the PDP-11/44,
as it supports the Commercial Instruction Set.

There are only so many ways to run four 74181 ALUs using microcode. You can have

different microcode word widths depending on what other bits you're twiddling in the 

overall CPU logic.

I'm pretty sure there are 74181 definitions available if you're doing this in a gate array.

That and the Field Maintenance Print Set should get you there if you're patient. Two

potential traps to be aware of are that some of the ECOs/FCOs are likely undocumented

(unless you have the appropriate DEC-O-LOG fiche) and that since the "wire lengths" are

so much shorter in a gate array than on an 11/70 backplane, you may need to waste

cells just to create appropriate delays to match the real hardware. The good news is that

the memory is asynchronous, so you can probably just pretend everything is "in cache"

and implement enough of the cache control and MK11 registers to make the diagnostics

happy.

The 11/44 microcode was revised several times after first customer ship due to bugs

found in the field. By the time I found one, they just went "too bad, so sad".

The 11/44 CIS microcode is on the smaller of the two 11/44 CIS boards and can be

read directly (those chips should be socketed). I forget if the FPU microcode is on

the FPU board or in the main CPU microcode and just skipped if the FPU isn't in-

stalled.

BTW, there's no reason an 11/70 can't have CIS - the design got to the point where it

was sent to Manufacturing and M-numbers were assigned and the microcode pro-

vided. One of the authors of the 11/74 CIS microcode is over on VCFED and may even

have a binary copy or listing. It was much faster than the 11/44 CIS, and also faster

than the VAX-11/780's CIS-type instructions. That's the reason for its demise. The

11/70MP group took over the 11/74 name after the 11/74 CIS was killed, which is

why you see various different labeling on pictures of the 11/70MP machines. The

thing that did in the 11/70MP was the complicated wiring and the need for Engineer-

ing to validate every sales order configuration before it could be accepted. So there 

are two reasons for the 11/74's demise, and both are true - just talking about differ-

ent hardware.

AFAIK, RSX-11M+ has code for both the 11/74 CIS and the 11/70MP multiprocess-

ing. I won't say "support" because as neither was released as a product, there isn't

anything to support.

[Edward Tottenham]

Hi Thalia,

I've been using two documents mostly, the engineering drawings and the processor manual.

The engineering drawings:

1170_Engineering_Drawings_revL_Mar1977.pdf

On page 5 there is a useful block diagram of the processor, with explanations as to what most of the bit-fields of the microinstruction do. This is followed by the flows, showing what is done in each microinstruction. On pages 75 to 80 is a listing of the actual microcode itself, though it's not always easy to read.

The KB11-C Processor Manual:

EK-KB11C-TM-001_1170procMan.pdf

Section II is the part which deals with the microcode, though you will need to use pretty much all of the manual if trying to implement a PDP 11/70.

I hope there's food for thought there

Ed

[Johnny Billquist]

Just a short comment on the last bit. RSX-11M-PLUS do have support for
the 11/74 (I'm running an emulated one). There is nothing related to CIS
in the kernel. If a machine have CIS, it's purely used by user level
software. Which of course is supported.

Johnny

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[Sytse van Slooten]

Guys

Of course the listings for the 11/70 diags are on bitsavers.  Joerg Hoppe scanned them a couple years ago.

Other than that, ASHC is a known bug in J-11 cpu's that don't have the FP accelerator (that fixes the bug). I stumbled over exactly the same issue. Storyline here:

and don't forget to read the background story https://simh.trailing-edge.com/docs/ucode_bugs.pdf

Cheers

Sytse

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[Henry Bent]

If you folks are heavily into PDP-11 development it might be worth joining the SIMH list if you haven't already.  There are several folks there who were heavily involved in DEC design, implementation, and subsequent simulation.

https://groups.io/g/simh

-Henry

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