[PATCH] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
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meg...@megous.com
Jun 4, 2019, 11:00:59 AM6/4/19
to linux...@googlegroups.com, Ondrej Jirman, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
From: Ondrej Jirman <meg...@megous.com>
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <meg...@megous.com>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 27554eaf6929..8d05d4f1f8a1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
- 0x1cc, BIT(0), 0);
+ 0x1ec, BIT(0), 0);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
--
2.21.0
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <meg...@megous.com>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 27554eaf6929..8d05d4f1f8a1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
- 0x1cc, BIT(0), 0);
+ 0x1ec, BIT(0), 0);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
--
2.21.0
Jernej Škrabec
Jun 4, 2019, 11:04:03 AM6/4/19
to linux...@googlegroups.com, meg...@megous.com, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
napisal(a):
Best regards,
Jernej
napisal(a):
> From: Ondrej Jirman <meg...@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
You should add Fixes tag and CC stable with this.
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
Best regards,
Jernej
Ondřej Jirman
Jun 4, 2019, 11:31:22 AM6/4/19
to Jernej Škrabec, linux...@googlegroups.com, Maxime Ripard, Michael Turquette, open list, Stephen Boyd, Chen-Yu Tsai, open list:COMMON CLK FRAMEWORK, moderated list:ARM/Allwinner sunXi SoC support
Hi Jernej,
Not necessary, since H6 IR is not yet supported on mainline.
regards,
o.
> Best regards,
> Jernej
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-ar...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
regards,
o.
> Best regards,
> Jernej
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-ar...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Jernej Škrabec
Jun 4, 2019, 11:35:52 AM6/4/19
to linux...@googlegroups.com, meg...@megous.com, Maxime Ripard, Michael Turquette, open list, Stephen Boyd, Chen-Yu Tsai, open list:COMMON CLK FRAMEWORK, moderated list:ARM/Allwinner sunXi SoC support
Hi!
Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
napisal(a):
existing driver (clk), fixes tag still apply.
Best regards,
Jernej
Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
napisal(a):
> Hi Jernej,
>
> On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> >
> > napisal(a):
> > > From: Ondrej Jirman <meg...@megous.com>
> > >
> > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > with the IR gate.
> > >
> > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > causing interrupt floods on H6 (because interrupt flags can't be
> > > cleared,
> > > due to IR module's bus being disabled).
> > >
> > > Signed-off-by: Ondrej Jirman <meg...@megous.com>
> >
> > You should add Fixes tag and CC stable with this.
>
> Not necessary, since H6 IR is not yet supported on mainline.
Well, CCing stable is probably really not necessary, but you are fixing bug in
>
> On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> >
> > napisal(a):
> > > From: Ondrej Jirman <meg...@megous.com>
> > >
> > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > with the IR gate.
> > >
> > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > causing interrupt floods on H6 (because interrupt flags can't be
> > > cleared,
> > > due to IR module's bus being disabled).
> > >
> > > Signed-off-by: Ondrej Jirman <meg...@megous.com>
> >
> > You should add Fixes tag and CC stable with this.
>
> Not necessary, since H6 IR is not yet supported on mainline.
existing driver (clk), fixes tag still apply.
Best regards,
Jernej
meg...@megous.com
Jun 4, 2019, 11:40:48 AM6/4/19
to linux...@googlegroups.com, Ondrej Jirman, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
From: Ondrej Jirman <meg...@megous.com>
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <meg...@megous.com>
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <meg...@megous.com>
Ondřej Jirman
Jun 4, 2019, 11:41:26 AM6/4/19
to Jernej Škrabec, linux...@googlegroups.com, Maxime Ripard, Michael Turquette, open list, Stephen Boyd, Chen-Yu Tsai, open list:COMMON CLK FRAMEWORK, moderated list:ARM/Allwinner sunXi SoC support
Hello Jernej,
On Tue, Jun 04, 2019 at 05:35:48PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
> napisal(a):
> > Hi Jernej,
> >
> > On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> > >
> > > napisal(a):
> > > > From: Ondrej Jirman <meg...@megous.com>
> > > >
> > > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > > with the IR gate.
> > > >
> > > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > > causing interrupt floods on H6 (because interrupt flags can't be
> > > > cleared,
> > > > due to IR module's bus being disabled).
> > > >
> > > > Signed-off-by: Ondrej Jirman <meg...@megous.com>
> > >
> > > You should add Fixes tag and CC stable with this.
> >
> > Not necessary, since H6 IR is not yet supported on mainline.
>
> Well, CCing stable is probably really not necessary, but you are fixing bug in
> existing driver (clk), fixes tag still apply.
Right, resent v2.
thank you and regards,
On Tue, Jun 04, 2019 at 05:35:48PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
> napisal(a):
> > Hi Jernej,
> >
> > On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> > >
> > > napisal(a):
> > > > From: Ondrej Jirman <meg...@megous.com>
> > > >
> > > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > > with the IR gate.
> > > >
> > > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > > causing interrupt floods on H6 (because interrupt flags can't be
> > > > cleared,
> > > > due to IR module's bus being disabled).
> > > >
> > > > Signed-off-by: Ondrej Jirman <meg...@megous.com>
> > >
> > > You should add Fixes tag and CC stable with this.
> >
> > Not necessary, since H6 IR is not yet supported on mainline.
>
> Well, CCing stable is probably really not necessary, but you are fixing bug in
> existing driver (clk), fixes tag still apply.
thank you and regards,
Clément Péron
Jun 4, 2019, 12:14:29 PM6/4/19
to meg...@megous.com, linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
<linux...@googlegroups.com> wrote:
>
> From: Ondrej Jirman <meg...@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 27554eaf6929..8d05d4f1f8a1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
> static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> - 0x1cc, BIT(0), 0);
> + 0x1ec, BIT(0), 0);
Just for information where did you find this information?
Using the vendor kernel or user manual?
Thanks,
Clément
>
> /* Information of IR(RX) mod clock is gathered from BSP source code */
> static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> --
> 2.21.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
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> For more options, visit https://groups.google.com/d/optout.
On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
<linux...@googlegroups.com> wrote:
>
> From: Ondrej Jirman <meg...@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 27554eaf6929..8d05d4f1f8a1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
> static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> - 0x1cc, BIT(0), 0);
> + 0x1ec, BIT(0), 0);
Using the vendor kernel or user manual?
Thanks,
Clément
>
> /* Information of IR(RX) mod clock is gathered from BSP source code */
> static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> --
> 2.21.0
>
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
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Ondřej Jirman
Jun 4, 2019, 12:21:48 PM6/4/19
to Clément Péron, linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
Hi Clément,
Informed guess. All gates and resets are in the same register. And
you can see below that reset register for w1 is 0x1ec. (reset register
for ir is 0x1cc)
regards,
o.
you can see below that reset register for w1 is 0x1ec. (reset register
for ir is 0x1cc)
regards,
o.
Clément Péron
Jun 4, 2019, 12:37:14 PM6/4/19
to Clément Péron, linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
Hi Ondrej,
Ok, I thinks this can confirm the value:
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/clk/sunxi/clk-sun50iw6.h#L161
Acked-by: Clément Péron <peron...@gmail.com>
Regards,
Clément
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/clk/sunxi/clk-sun50iw6.h#L161
Acked-by: Clément Péron <peron...@gmail.com>
Regards,
Clément
Maxime Ripard
Jun 5, 2019, 7:49:54 AM6/5/19
to meg...@megous.com, linux...@googlegroups.com, Chen-Yu Tsai, Michael Turquette, Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support, open list:COMMON CLK FRAMEWORK, open list
On Tue, Jun 04, 2019 at 05:40:36PM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman <meg...@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Applied, thanks
> From: Ondrej Jirman <meg...@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <meg...@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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