[PATCH v2 00/10] Allwinner A64/H6 IR support

[Clément Péron]

Hi,

A64 IR support series[1] pointed out that an A31 bindings should be
introduced.

This series introduce the A31 compatible bindings, then switch it on
the already existing board.

Finally introduce A64 and H6 support.

Regards,
Clément

[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464

Changes since v1:
- Document reset lines as required since A31
- Explain the memory mapping difference in commit log
- Fix misspelling "Allwiner" to "Allwinner"

Clément Péron (8):
dt-bindings: media: sunxi-ir: add A31 compatible
media: rc: sunxi: Add A31 compatible
ARM: dts: sunxi: prefer A31 instead of A13 for ir
dt-bindings: media: sunxi-ir: Add A64 compatible
dt-bindings: media: sunxi-ir: Add H6 compatible
arm64: dts: allwinner: h6: Add IR receiver node
arm64: dts: allwinner: h6: Enable IR on H6 boards
arm64: defconfig: enable IR SUNXI option

Igors Makejevs (1):
arm64: dts: allwinner: a64: Add IR node

Jernej Skrabec (1):
arm64: dts: allwinner: a64: Enable IR on Orange Pi Win

.../devicetree/bindings/media/sunxi-ir.txt | 11 +++++++++--
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/media/rc/sunxi-cir.c | 1 +
13 files changed, 68 insertions(+), 6 deletions(-)

--
2.20.1

[Clément Péron]

Allwiner A31 has a different memory mapping so add the compatible
we will need it later.

Signed-off-by: Clément Péron <peron...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 307e44714ea0..29ac33b68596 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -319,6 +319,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
static const struct of_device_id sunxi_ir_match[] = {
{ .compatible = "allwinner,sun4i-a10-ir", },
{ .compatible = "allwinner,sun5i-a13-ir", },
+ { .compatible = "allwinner,sun6i-a31-ir", },
{},
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);
--
2.20.1

[Clément Péron]

Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"
+ "allwinner,sun6i-a31-ir"
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.

+Required properties since A31:
+- resets : phandle + reset specifier pair
+
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
-- resets : phandle + reset specifier pair
- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
if missing.

--
2.20.1

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-

4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c04efad81bbc..110622b30796 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1351,7 +1351,7 @@
};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
resets = <&apb0_rst 1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 392b0cabbf0d..8d603f3309f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1067,7 +1067,7 @@

r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
- "allwinner,sun5i-a13-ir";
+ "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 0c1eec9000e3..310cd972ee5b 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1167,7 +1167,7 @@
};

r_ir: ir@8002000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..f0f5ba349c1b 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -822,7 +822,7 @@
};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
--
2.20.1

[Clément Péron]

There are some minor differences between A31 and A64 driver.

But A31 IR driver is compatible with A64.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +

1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 2e59a32a7e33..1dd287a4ab3a 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-ir"
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

--
2.20.1

[Clément Péron]

From: Igors Makejevs <git...@bwzone.com>

IR peripheral is completely compatible with A31 one.

Signed-off-by: Igors Makejevs <git...@bwzone.com>
Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 8c5b521e6389..b22b0aa89515 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1072,6 +1072,19 @@
#size-cells = <0>;
};

+ r_ir: ir@1f02000 {
+ compatible = "allwinner,sun50i-a64-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01f02000 0x400>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
+ };
+
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@@ -1099,6 +1112,11 @@
function = "s_i2c";
};

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL11";
+ function = "s_cir_rx";
+ };
+
r_pwm_pin: r-pwm-pin {
pins = "PL10";
function = "s_pwm";
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

OrangePi Win board contains IR receiver. Enable it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 510f661229dc..e05191b71adf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -180,6 +180,10 @@
status = "okay";
};

+&r_ir {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";

--
2.20.1

[Clément Péron]

There are some minor differences between A31 or A64 with H6 IR peripheral.

But A31 IR driver is compatible with H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt

index 1dd287a4ab3a..81eaf95fb764 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -6,6 +6,7 @@ Required properties:
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
"allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir"

[Clément Péron]

Allwinner H6 IR is similar to A31 and can use same driver.

Add support for it.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..649cbdfe452e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -647,6 +647,25 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+
+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL9";

+ function = "s_cir_rx";
+ };

+ };
+
+ r_ir: ir@7040000 {
+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;

+ clock-names = "apb", "ir";

+ resets = <&r_ccu RST_R_APB1_IR>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

};

r_i2c: i2c@7081400 {
--
2.20.1

[Clément Péron]

Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver.

Enable it in their device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++
3 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..680dc29cb089 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -232,6 +232,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec9b6a578e3f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -189,6 +189,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..ae12ee4fcc77 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -247,6 +247,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
--
2.20.1

[Clément Péron]

Enable CONFIG_IR_SUNXI option for ARM64, so that Allwinner A64/H6 SoCs
can use their IR receiver controller.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/configs/defconfig | 1 +

1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d583514258c..5128029100d2 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -460,6 +460,7 @@ CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
CONFIG_RC_DEVICES=y
CONFIG_IR_MESON=m
+CONFIG_IR_SUNXI=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
--
2.20.1

[Maxime Ripard]

Hi,

We should also move from reset_get_optional to the non optional
variant for the A31, and ignore it otherwise.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[Maxime Ripard]

On Mon, May 27, 2019 at 12:25:29AM +0200, Clément Péron wrote:
> Since A31, memory mapping of the IR driver has changed.
>
> Prefer the A31 bindings instead of A13.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
> arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
> arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-

Can you split the H3 in a separate patch? this will go through a
separate branch.

Thanks!

[Clément Péron]

Hi Maxime,

On Mon, 27 May 2019 at 09:47, Maxime Ripard <maxime...@bootlin.com> wrote:
>
> On Mon, May 27, 2019 at 12:25:29AM +0200, Clément Péron wrote:
> > Since A31, memory mapping of the IR driver has changed.
> >
> > Prefer the A31 bindings instead of A13.
> >
> > Signed-off-by: Clément Péron <peron...@gmail.com>
> > ---
> > arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
> > arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
> > arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
>
> Can you split the H3 in a separate patch? this will go through a
> separate branch.

Ok I will,
Thanks,
Clément

[Clément Péron]

Hi Maxime,

On Mon, 27 May 2019 at 09:47, Maxime Ripard <maxime...@bootlin.com> wrote:
>

Should this be done in this series ?
Thanks,
Clément

[Maxime Ripard]

On Mon, May 27, 2019 at 10:20:05AM +0200, Clément Péron wrote:
> Hi Maxime,
>
> On Mon, 27 May 2019 at 09:47, Maxime Ripard <maxime...@bootlin.com> wrote:
> >
> > Hi,
> >
> > On Mon, May 27, 2019 at 12:25:28AM +0200, Clément Péron wrote:
> > > Allwiner A31 has a different memory mapping so add the compatible
> > > we will need it later.
> > >
> > > Signed-off-by: Clément Péron <peron...@gmail.com>
> > > ---
> > > drivers/media/rc/sunxi-cir.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > > index 307e44714ea0..29ac33b68596 100644
> > > --- a/drivers/media/rc/sunxi-cir.c
> > > +++ b/drivers/media/rc/sunxi-cir.c
> > > @@ -319,6 +319,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
> > > static const struct of_device_id sunxi_ir_match[] = {
> > > { .compatible = "allwinner,sun4i-a10-ir", },
> > > { .compatible = "allwinner,sun5i-a13-ir", },
> > > + { .compatible = "allwinner,sun6i-a31-ir", },
> >
> > We should also move from reset_get_optional to the non optional
> > variant for the A31, and ignore it otherwise.
>
> Should this be done in this series ?

Yep, please

[Ondřej Jirman]

Hi Clément,

On Mon, May 27, 2019 at 12:25:26AM +0200, Clément Péron wrote:
> Hi,
>
> A64 IR support series[1] pointed out that an A31 bindings should be
> introduced.
>
> This series introduce the A31 compatible bindings, then switch it on
> the already existing board.
>
> Finally introduce A64 and H6 support.

Does H6 support actually work? I don't see any driver changes and last time
I tried with the exact same bindings, I got RCU stalls shortly after boot.

Enabling/disabling ir node was enough to trigger/stop the RCU stalls on H6.

regards,
o.

> _______________________________________________
> linux-arm-kernel mailing list
> linux-ar...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[Clément Péron]

Hi Ondřej,

On Mon, 27 May 2019 at 15:48, Ondřej Jirman <meg...@megous.com> wrote:
>
> Hi Clément,
>
> On Mon, May 27, 2019 at 12:25:26AM +0200, Clément Péron wrote:
> > Hi,
> >
> > A64 IR support series[1] pointed out that an A31 bindings should be
> > introduced.
> >
> > This series introduce the A31 compatible bindings, then switch it on
> > the already existing board.
> >
> > Finally introduce A64 and H6 support.
>
> Does H6 support actually work? I don't see any driver changes and last time
> I tried with the exact same bindings, I got RCU stalls shortly after boot.

Actually, I have tested only on H6 on my Beelink GS1 with a "NEC" remote.

I have manually toggle the protocols and do a simple cat in /dev/input/event0
# echo nec > /sys/class/rc/rc0/protocols
# cat /dev/input/event0 | hexdump
0000000 0093 0000 0000 0000 8bfb 0009 0000 0000
0000010 0004 0004 8028 0000 0093 0000 0000 0000
0000020 8bfb 0009 0000 0000 0000 0000 0000 0000
0000030 0093 0000 0000 0000 55be 000a 0000 0000
0000040 0004 0004 8028 0000 0093 0000 0000 0000
0000050 55be 000a 0000 0000 0000 0000 0000 0000
0000060 0093 0000 0000 0000 fa42 000d 0000 0000
0000070 0004 0004 8028 0000 0093 0000 0000 0000
0000080 fa42 000d 0000 0000 0000 0000 0000 0000
0000090 0093 0000 0000 0000 c41a 000e 0000 0000
00000a0 0004 0004 8028 0000 0093 0000 0000 0000
00000b0 c41a 000e 0000 0000 0000 0000 0000 0000


Which kernel did you test with? Do you have any log?

Thanks,
Clément

[Ondřej Jirman]

Hi Clément,

I tested with my kernel (https://megous.com/git/linux/log/?h=opi3-5.2). I also
tried with 5.1 and the same kernel build on H5, to exclude some early 5.2-rc
bugs and to see if this is H6 specific.

I'll try testing again with your patches, and get you some logs. But last time
they were not very informative.

regards,
o.

[Ondřej Jirman]

Hi Clément,

I'm testing on Orange Pi 3.

With your patches, I get kernel lockup after ~1 minute of use (ssh stops
responding/serial console stops responding). I don't have RC controller to test
the CIR. But just enabling the CIR causes kernel to hang shortly after boot.

I tried booting multiple times. Other results:

boot 2:

- ssh hangs even before connecting (ethernet crashes/is reset)

INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (1 GPs behind) idle=64a/0/0x3 softirq=4091/4091 fqs=2437
dwmac-sun8i 5020000.ethernet eth0: Reset adapter.
rcu: INFO: rcu_sched detected expedited stalls on CPUs/tasks: { 0-... } 5696 jiffies s: 81 root: 0x1/.
rcu: blocking rcu_node structures:
rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (1 GPs behind) idle=64a/0/0x3 softirq=4091/4091 fqs=9714
rcu: INFO: rcu_sched detected expedited stalls on CPUs/tasks: { 0-... } 21568 jiffies s: 81 root: 0x1/.
rcu: blocking rcu_node structures:
rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (1 GPs behind) idle=64a/0/0x3 softirq=4091/4091 fqs=17203

above messages appear regularly.

boot 3:

rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (9 GPs behind) idle=992/0/0x3 softirq=6123/6123 fqs=2600


Sometimes serial console keeps working. Sometimes it locks up too (but not
frequently). Storage locks up always (any program that was not run before
the crash can't be started and lock up the kernel hard, programs that
were executed prior, can be run again).


Exactly the same kernel build on H5 seems to work (or at least I was not able to
trigger the crash). So this seems to be limited to H6 for now.

I suspect that the crash occurs sooner if I vary the light (turn on/off the table
lamp light).

Without your patches, everything works fine on H6, and I never see
crashes/lockups.

I tired physically covering the IR receiver, and that helps preventing the
crash. As soon as I uncover it, the crash happens again in 1s or so:

rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (1 GPs behind) idle=4ea/0/0x3 softirq=4483/4484 fqs=2444
rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 0-....: (1 GPs behind) idle=4ea/0/0x3 softirq=4483/4484 fqs=9777

This time I got the hung task and reboot: (probably not directly related)

INFO: task find:560 blocked for more than 120 seconds.
Not tainted 5.2.0-rc2+ #7
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
find D 0 560 551 0x00000000
Call trace:
__switch_to+0x6c/0x90
__schedule+0x1f4/0x578
schedule+0x28/0xa8
io_schedule+0x18/0x38
__lock_page+0x12c/0x208
pagecache_get_page+0x238/0x2e8
__get_node_page+0x6c/0x310
f2fs_get_node_page+0x14/0x20
f2fs_iget+0x70/0xc60
f2fs_lookup+0xcc/0x218
__lookup_slow+0x78/0x160
lookup_slow+0x3c/0x60
walk_component+0x1e4/0x2e0
path_lookupat.isra.13+0x5c/0x1e0
filename_lookup.part.23+0x6c/0xe8
user_path_at_empty+0x4c/0x60
vfs_statx+0x78/0xd8
__se_sys_newfstatat+0x24/0x48
__arm64_sys_newfstatat+0x18/0x20
el0_svc_handler+0x9c/0x170
el0_svc+0x8/0xc
Kernel panic - not syncing: hung_task: blocked tasks
CPU: 1 PID: 34 Comm: khungtaskd Not tainted 5.2.0-rc2+ #7
Hardware name: OrangePi 3 (DT)
Call trace:
dump_backtrace+0x0/0xf8
show_stack+0x14/0x20
dump_stack+0xa8/0xcc
panic+0x124/0x2dc
proc_dohung_task_timeout_secs+0x0/0x40
kthread+0x120/0x128
ret_from_fork+0x10/0x18
SMP: stopping secondary CPUs
Kernel Offset: disabled
CPU features: 0x0002,20002000
Memory Limit: none
Rebooting in 3 seconds..


Meanwhile H5 based board now runs for 15 minutes without issues.

So to sum up:

- these crashes are definitely H6 IR related
- the same kernel, on H5 works
- covering the sensor prevents the crashes on H6

So we should probably hold on with the series, until this is figured out.

I have tried searching for differences between H3 and H6 BSPs. And there are some:

break;
case IR_IRQ_FIFO_SIZE:
- irq_reg = sunxi_smc_readl(IR_BASE+IR_RXINTE_REG);
- irq_reg |= IR_FIFO_32;
+ irq_reg = readl(reg_base + IR_RXINTE_REG);
+ irq_reg |= IR_FIFO_20;
break;
}

case IR_CLK_SAMPLE:
-#ifdef FPGA_SIM_CONFIG
- sample_reg |= 0x3<<0; /* Fsample = 24MHz/512 = 46875Hz (21.33us) */
-#else
- sample_reg |= IR_SAMPLE_128;
-#endif
+ sample_reg |= IR_SAMPLE_DEV;
break;

+ case IR_BOTH_PULSE_MODE:
+ ctrl_reg = readl(reg_base + IR_CTRL_REG);
+ ctrl_reg |= IR_BOTH_PULSE;
+ break;
+ case IR_LOW_PULSE_MODE:
+ ctrl_reg = readl(reg_base + IR_CTRL_REG);
+ ctrl_reg |= IR_LOW_PULSE;
+ break;
+ case IR_HIGH_PULSE_MODE:
+ ctrl_reg = readl(reg_base + IR_CTRL_REG);
+ ctrl_reg |= IR_HIGH_PULSE;
+ break;


0x0000 CIR_CTL

new bit 8 - CGPO
General Program Output (GPO) Control in CIR mode for TX Pin
0: Low level
1: High level

CIR_RXSTA 0x0030

RAC is just 13:8 instead of 14:8


I haven't looked deeper, because I have no use for IR on H6. But I hope this
helps. I can help testing patches if you like.

thank you and regards,
o.

[Clément Péron]

Hi Ondrej,

Thanks for testing, but I think it's more hardware related.
It seems that your IR is flooded or misconfigured for your board.
Could you add a simple print in the "sunxi_ir_irq"

If it's confirmed, maybe tweak the threshold configuration or
implement the new active_threshold will help.

With my hardware Beelink GS1 and on Jernej's board (A64) there is no issue.

I will disable all the other H6 boards until someone test it.

Regards,
Clément

[Ondřej Jirman]

Hi Clément,

On Mon, May 27, 2019 at 08:49:59PM +0200, Clément Péron wrote:
> Hi Ondrej,

Yes, I get flood of IRQs with status = 0x30. (after I turn on the lamp,
but it persists even after I turn it off and cover the IR sensor).

That's weird, because on H6 in CIR_RXSTA, bit 5 is undefined but corresponding
bit in CIR_RXINT is DRQ_EN (RX FIFO DMA Enable)

So I'm not sure what it could be flooded with and why IRQs keep being
fired, even with no sensor input after the FIFO is read.

regards,
o.

[Ondřej Jirman]

Hi Clément,

Interestingly, status also contains RAC, and it's 0 in this case. So the
interrupt if firing with "No available data in RX FIFO" repeatedly. Regardless
of input.

So there's something else up.

regards,
o.

> That's weird, because on H6 in CIR_RXSTA, bit 5 is undefined but corresponding
> bit in CIR_RXINT is DRQ_EN (RX FIFO DMA Enable)
>
> So I'm not sure what it could be flooded with and why IRQs keep being
> fired, even with no sensor input after the FIFO is read.
>
> regards,
> o.
>
> > If it's confirmed, maybe tweak the threshold configuration or
> > implement the new active_threshold will help.
> >
> > With my hardware Beelink GS1 and on Jernej's board (A64) there is no issue.
> >
> > I will disable all the other H6 boards until someone test it.
> >
> > Regards,
> > Clément
>

[Clément Péron]

Hi,

A64 IR support series[1] pointed out that an A31 bindings should be
introduced.

This series introduce the A31 compatible bindings, then switch it on
the already existing board.

Finally introduce A64 and H6 support.

I didn't enable the IR on other H6 boards as Ondrej reported an issue
on his board[2].

Regards,
Clément

[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464

[2] https://lkml.org/lkml/2019/5/27/321

Changes since v2:
- Disable IR for other H6 boards
- Split DTS patch for H3/H5
- Introduce IR quirks

Changes since v1:
- Document reset lines as required since A31
- Explain the memory mapping difference in commit log
- Fix misspelling "Allwiner" to "Allwinner"

Clément Péron (10):

dt-bindings: media: sunxi-ir: add A31 compatible

media: rc: Introduce sunxi_ir_quirks

media: rc: sunxi: Add A31 compatible

ARM: dts: sunxi: Prefer A31 bindings for IR
ARM: dts: sunxi: Prefer A31 bindings for IR

dt-bindings: media: sunxi-ir: Add A64 compatible
dt-bindings: media: sunxi-ir: Add H6 compatible
arm64: dts: allwinner: h6: Add IR receiver node

arm64: dts: allwinner: h6: Enable IR on Beelink GS1

arm64: defconfig: enable IR SUNXI option

Igors Makejevs (1):
arm64: dts: allwinner: a64: Add IR node

Jernej Skrabec (1):
arm64: dts: allwinner: a64: Enable IR on Orange Pi Win

.../devicetree/bindings/media/sunxi-ir.txt | 11 ++-

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 +++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++
arch/arm64/configs/defconfig | 1 +
drivers/media/rc/sunxi-cir.c | 70 +++++++++++++++----
11 files changed, 115 insertions(+), 20 deletions(-)

--
2.20.1

[Clément Péron]

This driver is used in various Allwinner SoC with different configuration.

Introduce a quirks struct to know the fifo size and if a reset is required.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++---------
1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 307e44714ea0..d02dcb6fd0a5 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -81,6 +81,17 @@
/* Time after which device stops sending data in ms */
#define SUNXI_IR_TIMEOUT 120

+/**
+ * struct sunxi_ir_quirks - Differences between SoC variants.
+ *
+ * @has_reset: SoC needs reset deasserted.
+ * @fifo_size: size of the fifo.
+ */
+struct sunxi_ir_quirks {
+ bool has_reset;
+ int fifo_size;
+};
+
struct sunxi_ir {
spinlock_t ir_lock;
struct rc_dev *rc;
@@ -143,6 +154,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)

struct device *dev = &pdev->dev;
struct device_node *dn = dev->of_node;
+ const struct sunxi_ir_quirks *quirks;
struct resource *res;
struct sunxi_ir *ir;
u32 b_clk_freq = SUNXI_IR_BASE_CLK;
@@ -151,12 +163,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (!ir)
return -ENOMEM;

+ quirks = of_device_get_match_data(&pdev->dev);
+ if (quirks == NULL) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+
spin_lock_init(&ir->ir_lock);

- if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
- ir->fifo_size = 64;
- else
- ir->fifo_size = 16;
+ ir->fifo_size = quirks->fifo_size;

/* Clock */
ir->apb_clk = devm_clk_get(dev, "apb");
@@ -173,13 +188,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
/* Base clock frequency (optional) */
of_property_read_u32(dn, "clock-frequency", &b_clk_freq);

- /* Reset (optional) */
- ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
- if (IS_ERR(ir->rst))
- return PTR_ERR(ir->rst);
- ret = reset_control_deassert(ir->rst);
- if (ret)
- return ret;
+ /* Reset */
+ if (quirks->has_reset) {
+ ir->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(ir->rst))
+ return PTR_ERR(ir->rst);
+ ret = reset_control_deassert(ir->rst);
+ if (ret)
+ return ret;
+ }

ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
@@ -316,10 +333,26 @@ static int sunxi_ir_remove(struct platform_device *pdev)
return 0;
}

+static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
+ .has_reset = false,
+ .fifo_size = 16,
+};
+
+static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
+ .has_reset = false,
+ .fifo_size = 64,
+};
+

static const struct of_device_id sunxi_ir_match[] = {

- { .compatible = "allwinner,sun4i-a10-ir", },
- { .compatible = "allwinner,sun5i-a13-ir", },
- {},
+ {
+ .compatible = "allwinner,sun4i-a10-ir",
+ .data = &sun4i_a10_ir_quirks,
+ },
+ {
+ .compatible = "allwinner,sun5i-a13-ir",
+ .data = &sun5i_a13_ir_quirks,
+ },
+ {}
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);

--
2.20.1

[Clément Péron]

Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt

@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"

+ "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

[Clément Péron]

Allwiner A31 has a different memory mapping so add the compatible
we will need it later.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/media/rc/sunxi-cir.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index d02dcb6fd0a5..0504ebfc831f 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -343,6 +343,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
.fifo_size = 64,
};

+static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
+ .has_reset = true,

+ .fifo_size = 64,
+};
+
static const struct of_device_id sunxi_ir_match[] = {

{
.compatible = "allwinner,sun4i-a10-ir",
@@ -352,6 +357,10 @@ static const struct of_device_id sunxi_ir_match[] = {
.compatible = "allwinner,sun5i-a13-ir",
.data = &sun5i_a13_ir_quirks,
},
+ {
+ .compatible = "allwinner,sun6i-a31-ir",
+ .data = &sun6i_a31_ir_quirks,
+ },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);
--
2.20.1

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c04efad81bbc..110622b30796 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1351,7 +1351,7 @@
};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;

clock-names = "apb", "ir";

resets = <&apb0_rst 1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 392b0cabbf0d..8d603f3309f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1067,7 +1067,7 @@

r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
- "allwinner,sun5i-a13-ir";
+ "allwinner,sun6i-a31-ir";

clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;

clock-names = "apb", "ir";

resets = <&r_ccu RST_APB0_IR>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 0c1eec9000e3..310cd972ee5b 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1167,7 +1167,7 @@
};

r_ir: ir@8002000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
--
2.20.1

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..f0f5ba349c1b 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi

@@ -822,7 +822,7 @@

};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;

--
2.20.1

[Clément Péron]

From: Igors Makejevs <git...@bwzone.com>

IR peripheral is completely compatible with A31 one.

Signed-off-by: Igors Makejevs <git...@bwzone.com>
Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 8c5b521e6389..b22b0aa89515 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1072,6 +1072,19 @@
#size-cells = <0>;
};

+ r_ir: ir@1f02000 {

+ compatible = "allwinner,sun50i-a64-ir",
+ "allwinner,sun6i-a31-ir";

+ reg = <0x01f02000 0x400>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;

+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

+ };
+
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@@ -1099,6 +1112,11 @@
function = "s_i2c";
};

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL11";

+ function = "s_cir_rx";
+ };
+

[Clément Péron]

There are some minor differences between A31 and A64 driver.

But A31 IR driver is compatible with A64.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +

1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 2e59a32a7e33..1dd287a4ab3a 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-ir"
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

OrangePi Win board contains IR receiver. Enable it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 510f661229dc..e05191b71adf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -180,6 +180,10 @@
status = "okay";
};

+&r_ir {
+ status = "okay";
+};
+

[Clément Péron]

Allwinner H6 IR is similar to A31 and can use same driver.

Add support for it.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..649cbdfe452e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -647,6 +647,25 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL9";

+ function = "s_cir_rx";
+ };

+ };
+
+ r_ir: ir@7040000 {

+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";

+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,

+ <&r_ccu CLK_IR>;

+ clock-names = "apb", "ir";

+ resets = <&r_ccu RST_R_APB1_IR>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

};

r_i2c: i2c@7081400 {
--
2.20.1

[Clément Péron]

There are some minor differences between A31 or A64 with H6 IR peripheral.

But A31 IR driver is compatible with H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt

index 1dd287a4ab3a..81eaf95fb764 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -6,6 +6,7 @@ Required properties:
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
"allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir"

[Clément Péron]

Beelink GS1 has an IR receiver.

Enable it in the device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..680dc29cb089 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -232,6 +232,10 @@
};
};

+&r_ir {
+ status = "okay";
+};
+

&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C

--
2.20.1

[Clément Péron]

Enable CONFIG_IR_SUNXI option for ARM64, so that Allwinner A64/H6 SoCs
can use their IR receiver controller.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/configs/defconfig | 1 +

1 file changed, 1 insertion(+)

[Clément Péron]

Hi Ondřej,

Really weird indeed...

I have pushed a new version, where I didn't enabled the support for
others H6 board and the cover letter include a link to this thread.

It would be great if other sunxi users could test this series, to
check if this issue in present in other OPi3 / Pine H64.

Regards,
Clément

>
> regards,
> o.
>
> > That's weird, because on H6 in CIR_RXSTA, bit 5 is undefined but corresponding
> > bit in CIR_RXINT is DRQ_EN (RX FIFO DMA Enable)
> >
> > So I'm not sure what it could be flooded with and why IRQs keep being
> > fired, even with no sensor input after the FIFO is read.
> >
> > regards,
> > o.
> >
> > > If it's confirmed, maybe tweak the threshold configuration or
> > > implement the new active_threshold will help.
> > >
> > > With my hardware Beelink GS1 and on Jernej's board (A64) there is no issue.
> > >
> > > I will disable all the other H6 boards until someone test it.
> > >
> > > Regards,
> > > Clément
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-ar...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190527195330.pugb7ypvnyv32fug%40core.my.home.
> For more options, visit https://groups.google.com/d/optout.

[Ondřej Jirman]

Hello Clément,

I don't know if this is enough. I'd rather prefer if the driver has a way
of detecting this situation and shutting the module down, at the very least,
instead of taking down the entire system with IRQ flood.

It may be detectable by checking RAC == 0 when RX FIFO available interrupt
flag is set.

Otherwise, this will eventually be forgotten (cover letters are not even stored
in git), and someone will fall into the trap again, after enabling r_ir on
their board, and end up chasing their tail for a day. I've initially only found
this is IR driver issue after a long unpleasant debugging session, chasing other
more obvious ideas (as when this happens there's absolutely nothing in the log
indicating this is IR issue).

regards,
o.

[Maxime Ripard]

Returning IRQ_NONE in the handler will disable the interrupt line
after 100,000 (I think?) occurences. That might be a good workaround,
but we definitely want to have a comment there :)

[Clément Péron]

Hi,

Thanks for the suggestion,

I will propose a patch to return IRQ_NONE if Fifo is empty when RA is setted.

Just a comment in the IRQ handling we are actually looking at the
RXSTA register and using the RXINT bit ?
Is there any reason for doing that ?

Thanks,
Clément

[Ondřej Jirman]

Hello Clément,

Please make a comment here, that this is known broken on some boards and may
result IRQ flood if enabled. Otherwise noone will know.

thanks,
o.

> r_i2c: i2c@7081400 {
> --
> 2.20.1

[Clément Péron]

Hi Ondrej,

I'm planning to send a v4 next week with the IRQ_NONE return as Maxime
suggested it.
https://github.com/clementperon/linux/tree/h6_ir_v4

But maybe we could also use the bit 5 of the IRQ status.

Regards, Clement

[Ondřej Jirman]

Hello Clément,

Thanks, that's nice, but that will not make the HW work. That will just disable
it. The comment is still necessary.

thank you,
o.

> Regards, Clement
>
> >
> > thanks,
> > o.
> >
> > > r_i2c: i2c@7081400 {
> > > --
> > > 2.20.1
> > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-ar...@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com.

> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCce7nHSktVsDKcR8GLRpD3WrN5yP3Nb_Hbu_Q9NjUQbSMw%40mail.gmail.com.

[Clément Péron]

Hi Ondrej,

I have pushed a new version on my github.
https://github.com/clementperon/linux/commits/h6_ir_v4

I will submit it, if you are ok with it.

Thanks,
Clément

[Ondřej Jirman]

Hi Clément,

the changes make it worse. Console is flooded with "Temporarily disable IRQ"
and other symptoms are the same as I described before. Interrupts are not
disabled in a any reasonable time. (I've waited for more > 5mins already.)

You probably need to disable interrupts right away, not wait for 100k failures.

thank you and regards,
o.

[Ondřej Jirman]

Hi Clément,

Hmm, this is what the registers look like post-probe:

R_CIR:
0x07040000 : 00000030
0x07040004 : 00000030
0x07040008 : 00000030
0x0704000c : 00000030
0x07040010 : 00000030
0x07040014 : 00000030
0x07040018 : 00000030
0x0704001c : 00000030
0x07040020 : 00000030
0x07040024 : 00000030
0x07040028 : 00000030
0x0704002c : 00000030
0x07040030 : 00000030
0x07040034 : 00000030
0x07040038 : 00000030
0x0704003c : 00000030
0x07040040 : 00000030
0x07040044 : 00000030
0x07040048 : 00000030
0x0704004c : 00000030
0x07040050 : 00000030
0x07040054 : 00000030
0x07040058 : 00000030
0x0704005c : 00000030
0x07040060 : 00000030
0x07040064 : 00000030
0x07040068 : 00000030
0x0704006c : 00000030
0x07040070 : 00000030
0x07040074 : 00000030
0x07040078 : 00000030
0x0704007c : 00000030
0x07040080 : 00000030
0x07040084 : 00000030
0x07040088 : 00000030
0x0704008c : 00000030
0x07040090 : 00000030
0x07040094 : 00000030
0x07040098 : 00000030
0x0704009c : 00000030
0x070400a0 : 00000030
0x070400a4 : 00000030
0x070400a8 : 00000030
0x070400ac : 00000030
0x070400b0 : 00000030
0x070400b4 : 00000030
0x070400b8 : 00000030
0x070400bc : 00000030
0x070400c0 : 00000030
0x070400c4 : 00000030
0x070400c8 : 00000030
0x070400cc : 00000030
0x070400d0 : 00000030
0x070400d4 : 00000030
0x070400d8 : 00000030
0x070400dc : 00000030
0x070400e0 : 00000030
0x070400e4 : 00000030
0x070400e8 : 00000030
0x070400ec : 00000030
0x070400f0 : 00000030
0x070400f4 : 00000030
0x070400f8 : 00000030
0x070400fc : 00000030

Clearly not right. It's just the R_CIR module, other modules have normal values.

I've checked:
0x070101c0 : 81000002
(IR clock config register)
0x070101cc : 00010000
(IR reset/bus clk gate reg)

static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
r_mod0_default_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);

static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);

[RST_R_APB1_IR] = { 0x1cc, BIT(16) },

So parent clock seems to be OK. But gate clock is not enabled, so the bus
is not working.

And look at this!!:

static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
0x1cc, BIT(0), 0);

So, it's wrong w1 gate config!

You can drop your changes, because I've probbably found the root cause.

regards,
o.

[Ondřej Jirman]

On Tue, May 28, 2019 at 06:14:31PM +0200, Clément Péron wrote:
> Allwiner A31 has a different memory mapping so add the compatible
> we will need it later.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> drivers/media/rc/sunxi-cir.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> index d02dcb6fd0a5..0504ebfc831f 100644
> --- a/drivers/media/rc/sunxi-cir.c
> +++ b/drivers/media/rc/sunxi-cir.c
> @@ -343,6 +343,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
> .fifo_size = 64,
> };
>
> +static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
> + .has_reset = true,
> + .fifo_size = 64,
> +};
> +

BTW, H6 BSP uses FIFO size 40:

https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/media/rc/sunxi-ir-dev.c#L290

Have you tried filling the fifo with over 40 words on H6, to see if it works?

I know it's docummented as having 64 words in the manual, so maybe Allwiner
just didn't care enough to make the driver configurable, and the H6
FIFO really has that depth.

regards,
o.

> static const struct of_device_id sunxi_ir_match[] = {
> {
> .compatible = "allwinner,sun4i-a10-ir",
> @@ -352,6 +357,10 @@ static const struct of_device_id sunxi_ir_match[] = {
> .compatible = "allwinner,sun5i-a13-ir",
> .data = &sun5i_a13_ir_quirks,
> },
> + {
> + .compatible = "allwinner,sun6i-a31-ir",
> + .data = &sun6i_a31_ir_quirks,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, sunxi_ir_match);
> --
> 2.20.1
>
>

[Clément Péron]

Hi Ondrej,

Nice to see that you have found the issue, but I don't understand why
It's working on my board on not on yours.

Regards,
Clément

[Clément Péron]

Hi,

On Tue, 4 Jun 2019 at 16:54, Ondřej Jirman <meg...@megous.com> wrote:
>
> On Tue, May 28, 2019 at 06:14:31PM +0200, Clément Péron wrote:
> > Allwiner A31 has a different memory mapping so add the compatible
> > we will need it later.
> >
> > Signed-off-by: Clément Péron <peron...@gmail.com>
> > ---
> > drivers/media/rc/sunxi-cir.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
> > index d02dcb6fd0a5..0504ebfc831f 100644
> > --- a/drivers/media/rc/sunxi-cir.c
> > +++ b/drivers/media/rc/sunxi-cir.c
> > @@ -343,6 +343,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
> > .fifo_size = 64,
> > };
> >
> > +static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
> > + .has_reset = true,
> > + .fifo_size = 64,
> > +};
> > +
>
> BTW, H6 BSP uses FIFO size 40:
>
> https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/media/rc/sunxi-ir-dev.c#L290
>
> Have you tried filling the fifo with over 40 words on H6, to see if it works?

No I didn't try this, but I trust more the user manual than the driver.
And I don't see why they would have reduce the fifo size in the new generation.
Anyway, I will be able to test that at the end of the week.

Regards,
Clément

[Ondřej Jirman]

Hi Clément,

Maybe you use modules? I have a builtin driver.

That may change initialization order. It would disable unused gates first, and
when you load the module later from userpsace then it would enable the gate.

If builtin, then it would enable IR gate first, and then disable the unused
gates (W1 in this case), later on when entering userspace.

Anyway, I can confirm that now, when I turn on the light in the room, I get
around 10 interrupts with empty FIFO and than it stops.

It doesn't cause the flood anymore.

regards,
o.

[Clément Péron]

Hi Ondrej,

Correct,

>
> That may change initialization order. It would disable unused gates first, and
> when you load the module later from userpsace then it would enable the gate.
>
> If builtin, then it would enable IR gate first, and then disable the unused
> gates (W1 in this case), later on when entering userspace.

Thanks for the explanation it makes sense.

>
> Anyway, I can confirm that now, when I turn on the light in the room, I get
> around 10 interrupts with empty FIFO and than it stops.

Ok I will push a V4 with just the introduction of the RXSTA.

Regards,
Clément

[Clément Péron]

Hi,

A64 IR support series[1] pointed out that an A31 bindings should be
introduced.

This series introduce the A31 compatible bindings, then switch it on
the already existing board.

Finally introduce A64 and H6 support.

I have reenable the other H6 boards IR support as Ondrej solve the issue.

Regards,
Clément

[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464
[2] https://lkml.org/lkml/2019/5/27/321
[3] https://patchwork.kernel.org/patch/10975563/

Changes since v3:
- Reenable IR for other H6 boards
- Add RXSTA bits definition
- Add Sean Young's "Acked-by" tags

Changes since v2:
- Disable IR for other H6 boards
- Split DTS patch for H3/H5
- Introduce IR quirks

Changes since v1:
- Document reset lines as required since A31
- Explain the memory mapping difference in commit log
- Fix misspelling "Allwiner" to "Allwinner"
Clément Péron (11):
dt-bindings: media: sunxi-ir: Add A31 compatible
media: rc: Introduce sunxi_ir_quirks
media: rc: sunxi: Add A31 compatible
media: rc: sunxi: Add RXSTA bits definition
ARM: dts: sunxi: Prefer A31 bindings for IR
ARM: dts: sunxi: Prefer A31 bindings for IR
dt-bindings: media: sunxi-ir: Add A64 compatible
dt-bindings: media: sunxi-ir: Add H6 compatible
arm64: dts: allwinner: h6: Add IR receiver node
arm64: dts: allwinner: h6: Enable IR on H6 boards
arm64: defconfig: Enable IR SUNXI option

Igors Makejevs (1):
arm64: dts: allwinner: a64: Add IR node

Jernej Skrabec (1):
arm64: dts: allwinner: a64: Enable IR on Orange Pi Win

.../devicetree/bindings/media/sunxi-ir.txt | 11 ++-

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-

arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 4 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 +
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 4 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 ++++
arch/arm64/configs/defconfig | 1 +
drivers/media/rc/sunxi-cir.c | 88 ++++++++++++++-----
13 files changed, 135 insertions(+), 26 deletions(-)

--
2.20.1

[Clément Péron]

Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"
+ "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.

+Required properties since A31:
+- resets : phandle + reset specifier pair
+
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
-- resets : phandle + reset specifier pair
- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
if missing.

--
2.20.1

[Clément Péron]

Allwiner A31 has a different memory mapping so add the compatible
we will need it later.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

drivers/media/rc/sunxi-cir.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index d02dcb6fd0a5..0504ebfc831f 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -343,6 +343,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
.fifo_size = 64,
};

+static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
+ .has_reset = true,
+ .fifo_size = 64,
+};
+

[Clément Péron]

This driver is used in various Allwinner SoC with different configuration.

Introduce a quirks struct to know the fifo size and if a reset is required.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++---------
1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 307e44714ea0..d02dcb6fd0a5 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -81,6 +81,17 @@
/* Time after which device stops sending data in ms */
#define SUNXI_IR_TIMEOUT 120

+/**
+ * struct sunxi_ir_quirks - Differences between SoC variants.
+ *
+ * @has_reset: SoC needs reset deasserted.
+ * @fifo_size: size of the fifo.
+ */
+struct sunxi_ir_quirks {
+ bool has_reset;
+ int fifo_size;
+};
+
struct sunxi_ir {
spinlock_t ir_lock;
struct rc_dev *rc;
@@ -143,6 +154,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)

struct device *dev = &pdev->dev;
struct device_node *dn = dev->of_node;
+ const struct sunxi_ir_quirks *quirks;
struct resource *res;
struct sunxi_ir *ir;
u32 b_clk_freq = SUNXI_IR_BASE_CLK;
@@ -151,12 +163,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (!ir)
return -ENOMEM;

+ quirks = of_device_get_match_data(&pdev->dev);
+ if (quirks == NULL) {
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
+
spin_lock_init(&ir->ir_lock);

- if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
- ir->fifo_size = 64;
- else
- ir->fifo_size = 16;
+ ir->fifo_size = quirks->fifo_size;

/* Clock */
ir->apb_clk = devm_clk_get(dev, "apb");
@@ -173,13 +188,15 @@ static int sunxi_ir_probe(struct platform_device *pdev)
/* Base clock frequency (optional) */
of_property_read_u32(dn, "clock-frequency", &b_clk_freq);

- /* Reset (optional) */
- ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
- if (IS_ERR(ir->rst))
- return PTR_ERR(ir->rst);
- ret = reset_control_deassert(ir->rst);
- if (ret)
- return ret;
+ /* Reset */
+ if (quirks->has_reset) {
+ ir->rst = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(ir->rst))
+ return PTR_ERR(ir->rst);
+ ret = reset_control_deassert(ir->rst);
+ if (ret)
+ return ret;
+ }

ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
@@ -316,10 +333,26 @@ static int sunxi_ir_remove(struct platform_device *pdev)
return 0;
}

+static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {
+ .has_reset = false,
+ .fifo_size = 16,
+};
+
+static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
+ .has_reset = false,

+ .fifo_size = 64,
+};
+
static const struct of_device_id sunxi_ir_match[] = {

- { .compatible = "allwinner,sun4i-a10-ir", },
- { .compatible = "allwinner,sun5i-a13-ir", },
- {},
+ {
+ .compatible = "allwinner,sun4i-a10-ir",
+ .data = &sun4i_a10_ir_quirks,
+ },
+ {
+ .compatible = "allwinner,sun5i-a13-ir",
+ .data = &sun5i_a13_ir_quirks,
+ },
+ {}
};
MODULE_DEVICE_TABLE(of, sunxi_ir_match);

--
2.20.1

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c04efad81bbc..110622b30796 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1351,7 +1351,7 @@
};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;

clock-names = "apb", "ir";

resets = <&apb0_rst 1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 392b0cabbf0d..8d603f3309f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1067,7 +1067,7 @@

r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
- "allwinner,sun5i-a13-ir";
+ "allwinner,sun6i-a31-ir";
clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;

clock-names = "apb", "ir";

resets = <&r_ccu RST_APB0_IR>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 0c1eec9000e3..310cd972ee5b 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1167,7 +1167,7 @@
};

r_ir: ir@8002000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
--
2.20.1

[Clément Péron]

We are using RXINT bits definition when looking at RXSTA register.

These bits are equal but it's not really proper.

Introduce the RXSTA bits and use them to have coherency.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 0504ebfc831f..572bd2257d35 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -48,11 +48,11 @@

/* Rx Interrupt Enable */
#define SUNXI_IR_RXINT_REG 0x2C
-/* Rx FIFO Overflow */
+/* Rx FIFO Overflow Interrupt Enable */
#define REG_RXINT_ROI_EN BIT(0)
-/* Rx Packet End */
+/* Rx Packet End Interrupt Enable */
#define REG_RXINT_RPEI_EN BIT(1)
-/* Rx FIFO Data Available */
+/* Rx FIFO Data Available Interrupt Enable */
#define REG_RXINT_RAI_EN BIT(4)

/* Rx FIFO available byte level */
@@ -60,6 +60,12 @@

/* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG 0x30
+/* Rx FIFO Overflow */
+#define REG_RXSTA_ROI BIT(0)
+/* Rx Packet End */
+#define REG_RXSTA_RPE BIT(1)
+/* Rx FIFO Data Available */
+#define REG_RXSTA_RA BIT(4)
/* RX FIFO Get Available Counter */
#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
/* Clear all interrupt status value */
@@ -119,7 +125,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* clean all pending statuses */
writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);

- if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
+ if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
/* How many messages in fifo */
rc = REG_RXSTA_GET_AC(status);
/* Sanity check */
@@ -135,9 +141,9 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
}
}

- if (status & REG_RXINT_ROI_EN) {
+ if (status & REG_RXSTA_ROI) {
ir_raw_event_reset(ir->rc);
- } else if (status & REG_RXINT_RPEI_EN) {
+ } else if (status & REG_RXSTA_RPE) {
ir_raw_event_set_idle(ir->rc, true);
ir_raw_event_handle(ir->rc);
}
--
2.20.1

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..f0f5ba349c1b 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -822,7 +822,7 @@

};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;

--
2.20.1

[Clément Péron]

There are some minor differences between A31 and A64 driver.

But A31 IR driver is compatible with A64.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +

1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 2e59a32a7e33..1dd287a4ab3a 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-ir"
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

--
2.20.1

[Clément Péron]

From: Igors Makejevs <git...@bwzone.com>

IR peripheral is completely compatible with A31 one.

Signed-off-by: Igors Makejevs <git...@bwzone.com>
Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 8c5b521e6389..b22b0aa89515 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1072,6 +1072,19 @@
#size-cells = <0>;
};

+ r_ir: ir@1f02000 {
+ compatible = "allwinner,sun50i-a64-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01f02000 0x400>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

+ };
+
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@@ -1099,6 +1112,11 @@
function = "s_i2c";
};

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL11";

+ function = "s_cir_rx";
+ };
+

r_pwm_pin: r-pwm-pin {
pins = "PL10";
function = "s_pwm";
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

OrangePi Win board contains IR receiver. Enable it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 510f661229dc..e05191b71adf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -180,6 +180,10 @@
status = "okay";
};

+&r_ir {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";

--
2.20.1

[Clément Péron]

There are some minor differences between A31 or A64 with H6 IR peripheral.

But A31 IR driver is compatible with H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt

index 1dd287a4ab3a..81eaf95fb764 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -6,6 +6,7 @@ Required properties:
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
"allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"
+ "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir"

[Clément Péron]

Allwinner H6 IR is similar to A31 and can use same driver.

Add support for it.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..649cbdfe452e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -647,6 +647,25 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL9";

+ function = "s_cir_rx";
+ };

+ };
+
+ r_ir: ir@7040000 {

+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";

+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,

+ <&r_ccu CLK_IR>;

+ clock-names = "apb", "ir";

+ resets = <&r_ccu RST_R_APB1_IR>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

};

r_i2c: i2c@7081400 {
--
2.20.1

[Clément Péron]

Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver.

Enable it in their device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++
3 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..680dc29cb089 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -232,6 +232,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec9b6a578e3f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -189,6 +189,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..ae12ee4fcc77 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -247,6 +247,10 @@

};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
--
2.20.1

[Clément Péron]

Enable CONFIG_IR_SUNXI option for ARM64, so that Allwinner A64/H6 SoCs
can use their IR receiver controller.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/configs/defconfig | 1 +

1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d583514258c..5128029100d2 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -460,6 +460,7 @@ CONFIG_RC_CORE=m
CONFIG_RC_DECODERS=y
CONFIG_RC_DEVICES=y
CONFIG_IR_MESON=m
+CONFIG_IR_SUNXI=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
--
2.20.1

[Maxime Ripard]

On Tue, Jun 04, 2019 at 06:29:47PM +0200, Clément Péron wrote:
> Allwinner A31 has introduced a new memory mapping and a
> reset line.
>
> The difference in memory mapping are :
>
> - In the configure register there is a new sample bit
> and Allwinner has introduced the active threshold feature.
>
> - In the status register a new STAT bit is present.
>
> Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
> and on new SoCs like A64/H6.
> This is actually not an issue as these bits are togglable and new
> SoCs have a dedicated bindings.
>
> Introduce this bindings to make a difference since this generation.
> And declare the reset line required since A31.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>

Acked-by: Maxime Ripard <maxime...@bootlin.com>

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[Maxime Ripard]

On Tue, Jun 04, 2019 at 06:29:48PM +0200, Clément Péron wrote:
> This driver is used in various Allwinner SoC with different configuration.
>
> Introduce a quirks struct to know the fifo size and if a reset is required.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>

[Maxime Ripard]

On Tue, Jun 04, 2019 at 06:29:49PM +0200, Clément Péron wrote:
> Allwiner A31 has a different memory mapping so add the compatible
> we will need it later.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>

[Maxime Ripard]

I'm fine with it on principle, but if the consistency needs to be
maintained then we could just reuse the above defines

[Clément Péron]

Hi Maxime,

There is no comment why we can reuse them, they can also be some wrong
case for example the RXINT_DRQ_EN bit is not present in RXSTA and same
for STAT bit present in RXSTA and not present in RXINT.

I have discover and read this code a month ago and this logic is
really not obvious nor explain.

Maybe this hack could be done when we will introduce a quirks, but for
the moment I really think that it's more proper and readable to
introduce them properly.

Regards,
Clément

[Maxime Ripard]

I don't think we understood each other :)

I was talking about having something like

#define REG_RXSTA_ROI REG_RXINT_ROI_EN

[Clément Péron]

Ok, I will send an update.

Thanks for the review,
Clément

[Clément Péron]

Hi,

A64 IR support series[1] pointed out that an A31 bindings should be
introduced.

This series introduce the A31 compatible bindings, then switch it on
the already existing board.

Finally introduce A64 and H6 support.

I have reenable the other H6 boards IR support as Ondrej solve the issue.

Regards,
Clément

[1] https://lore.kernel.org/patchwork/patch/1031390/#1221464
[2] https://lkml.org/lkml/2019/5/27/321
[3] https://patchwork.kernel.org/patch/10975563/

Changes since v4:
- Reuse defines for RXSTA bits definition

Changes since v3:
- Reenable IR for other H6 boards
- Add RXSTA bits definition
- Add Sean Young's "Acked-by" tags

Changes since v2:
- Disable IR for other H6 boards
- Split DTS patch for H3/H5
- Introduce IR quirks

Clément Péron (11):
dt-bindings: media: sunxi-ir: Add A31 compatible
media: rc: Introduce sunxi_ir_quirks
media: rc: sunxi: Add A31 compatible
media: rc: sunxi: Add RXSTA bits definition
ARM: dts: sunxi: Prefer A31 bindings for IR
ARM: dts: sunxi: Prefer A31 bindings for IR
dt-bindings: media: sunxi-ir: Add A64 compatible
dt-bindings: media: sunxi-ir: Add H6 compatible
arm64: dts: allwinner: h6: Add IR receiver node
arm64: dts: allwinner: h6: Enable IR on H6 boards
arm64: defconfig: Enable IR SUNXI option

Igors Makejevs (1):
arm64: dts: allwinner: a64: Add IR node

Jernej Skrabec (1):
arm64: dts: allwinner: a64: Enable IR on Orange Pi Win

.../devicetree/bindings/media/sunxi-ir.txt | 11 ++-

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-

[Clément Péron]

Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
Acked-by: Maxime Ripard <maxime...@bootlin.com>

---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt

@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"

+ "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

[Clément Péron]

This driver is used in various Allwinner SoC with different configuration.

Introduce a quirks struct to know the fifo size and if a reset is required.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++---------
1 file changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 307e44714ea0..d02dcb6fd0a5 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c

[Clément Péron]

Allwiner A31 has a different memory mapping so add the compatible
we will need it later.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
Acked-by: Maxime Ripard <maxime...@bootlin.com>
---

drivers/media/rc/sunxi-cir.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index d02dcb6fd0a5..0504ebfc831f 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c

@@ -343,6 +343,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {
.fifo_size = 64,
};

+static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {
+ .has_reset = true,

+ .fifo_size = 64,
+};
+
static const struct of_device_id sunxi_ir_match[] = {

{
.compatible = "allwinner,sun4i-a10-ir",
@@ -352,6 +357,10 @@ static const struct of_device_id sunxi_ir_match[] = {
.compatible = "allwinner,sun5i-a13-ir",
.data = &sun5i_a13_ir_quirks,

},
+ {

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>

---

arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index c04efad81bbc..110622b30796 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi

@@ -1351,7 +1351,7 @@

};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

clocks = <&apb0_gates 1>, <&ir_clk>;

clock-names = "apb", "ir";

resets = <&apb0_rst 1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 392b0cabbf0d..8d603f3309f2 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1067,7 +1067,7 @@

r_cir: ir@1f02000 {
compatible = "allwinner,sun8i-a83t-ir",
- "allwinner,sun5i-a13-ir";
+ "allwinner,sun6i-a31-ir";

clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;

clock-names = "apb", "ir";

resets = <&r_ccu RST_APB0_IR>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 0c1eec9000e3..310cd972ee5b 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1167,7 +1167,7 @@
};

r_ir: ir@8002000 {

- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
--
2.20.1

[Clément Péron]

We are using RXINT bits definition when looking at RXSTA register.

These bits are equal but it's not really proper.

Introduce the RXSTA bits and use them to have coherency.

Signed-off-by: Clément Péron <peron...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 0504ebfc831f..5690d0bd51bc 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c

@@ -48,11 +48,11 @@

/* Rx Interrupt Enable */
#define SUNXI_IR_RXINT_REG 0x2C
-/* Rx FIFO Overflow */
+/* Rx FIFO Overflow Interrupt Enable */
#define REG_RXINT_ROI_EN BIT(0)
-/* Rx Packet End */
+/* Rx Packet End Interrupt Enable */
#define REG_RXINT_RPEI_EN BIT(1)
-/* Rx FIFO Data Available */
+/* Rx FIFO Data Available Interrupt Enable */
#define REG_RXINT_RAI_EN BIT(4)

/* Rx FIFO available byte level */
@@ -60,6 +60,12 @@

/* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG 0x30
+/* Rx FIFO Overflow */

+#define REG_RXSTA_ROI REG_RXINT_ROI_EN

+/* Rx Packet End */

+#define REG_RXSTA_RPE REG_RXINT_RPEI_EN

+/* Rx FIFO Data Available */

+#define REG_RXSTA_RA REG_RXINT_RAI_EN

[Clément Péron]

Since A31, memory mapping of the IR driver has changed.

Prefer the A31 bindings instead of A13.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..f0f5ba349c1b 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi

@@ -822,7 +822,7 @@

};

ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";

clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;

--
2.20.1

[Clément Péron]

There are some minor differences between A31 and A64 driver.

But A31 IR driver is compatible with A64.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +

1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 2e59a32a7e33..1dd287a4ab3a 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt

@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-ir"
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"

+ "allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"

- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;

--
2.20.1

[Clément Péron]

From: Igors Makejevs <git...@bwzone.com>

IR peripheral is completely compatible with A31 one.

Signed-off-by: Igors Makejevs <git...@bwzone.com>
Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 8c5b521e6389..b22b0aa89515 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1072,6 +1072,19 @@
#size-cells = <0>;
};

+ r_ir: ir@1f02000 {

+ compatible = "allwinner,sun50i-a64-ir",
+ "allwinner,sun6i-a31-ir";

+ reg = <0x01f02000 0x400>;
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;

+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

+ };
+
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
@@ -1099,6 +1112,11 @@
function = "s_i2c";
};

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL11";

+ function = "s_cir_rx";
+ };
+

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

OrangePi Win board contains IR receiver. Enable it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 510f661229dc..e05191b71adf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -180,6 +180,10 @@
status = "okay";
};

+&r_ir {
+ status = "okay";
+};
+

[Clément Péron]

There are some minor differences between A31 or A64 with H6 IR peripheral.

But A31 IR driver is compatible with H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt

index 1dd287a4ab3a..81eaf95fb764 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt

@@ -6,6 +6,7 @@ Required properties:
"allwinner,sun5i-a13-ir"
"allwinner,sun6i-a31-ir"
"allwinner,sun50i-a64-ir", "allwinner,sun6i-a31-ir"

+ "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir"

[Clément Péron]

Allwinner H6 IR is similar to A31 and can use same driver.

Add support for it.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..649cbdfe452e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -647,6 +647,25 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+

+ r_ir_rx_pin: r-ir-rx-pin {
+ pins = "PL9";

+ function = "s_cir_rx";
+ };

+ };
+
+ r_ir: ir@7040000 {

+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";

+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,

+ <&r_ccu CLK_IR>;

+ clock-names = "apb", "ir";

+ resets = <&r_ccu RST_R_APB1_IR>;

+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";

};

r_i2c: i2c@7081400 {
--
2.20.1

[Clément Péron]

Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver.

Enable it in their device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++
3 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..680dc29cb089 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -232,6 +232,10 @@
};
};

+&r_ir {
+ status = "okay";
+};
+

&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec9b6a578e3f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -189,6 +189,10 @@
};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";

pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..ae12ee4fcc77 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -247,6 +247,10 @@
};
};

+&r_ir {
+ status = "okay";
+};
+

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
--
2.20.1

[Clément Péron]

Enable CONFIG_IR_SUNXI option for ARM64, so that Allwinner A64/H6 SoCs
can use their IR receiver controller.

Signed-off-by: Clément Péron <peron...@gmail.com>
Acked-by: Sean Young <se...@mess.org>
---

arch/arm64/configs/defconfig | 1 +

1 file changed, 1 insertion(+)

[Maxime Ripard]

On Sat, Jun 08, 2019 at 01:10:51AM +0200, Clément Péron wrote:
> We are using RXINT bits definition when looking at RXSTA register.
>
> These bits are equal but it's not really proper.
>
> Introduce the RXSTA bits and use them to have coherency.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>

Acked-by: Maxime Ripard <maxime...@bootlin.com>

[Rob Herring]

On Tue, 28 May 2019 18:14:29 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> Allwinner A31 has introduced a new memory mapping and a
> reset line.
>
> The difference in memory mapping are :
>
> - In the configure register there is a new sample bit
> and Allwinner has introduced the active threshold feature.
>
> - In the status register a new STAT bit is present.
>
> Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
> and on new SoCs like A64/H6.
> This is actually not an issue as these bits are togglable and new
> SoCs have a dedicated bindings.
>
> Introduce this bindings to make a difference since this generation.
> And declare the reset line required since A31.
>

> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---

> Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>

Reviewed-by: Rob Herring <ro...@kernel.org>

[Rob Herring]

On Sat, 8 Jun 2019 01:10:48 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> Allwinner A31 has introduced a new memory mapping and a
> reset line.
>
> The difference in memory mapping are :
>
> - In the configure register there is a new sample bit
> and Allwinner has introduced the active threshold feature.
>
> - In the status register a new STAT bit is present.
>
> Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
> and on new SoCs like A64/H6.
> This is actually not an issue as these bits are togglable and new
> SoCs have a dedicated bindings.
>
> Introduce this bindings to make a difference since this generation.
> And declare the reset line required since A31.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>
> Acked-by: Maxime Ripard <maxime...@bootlin.com>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>

Reviewed-by: Rob Herring <ro...@kernel.org>

[Rob Herring]

On Sat, 8 Jun 2019 01:10:54 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> There are some minor differences between A31 and A64 driver.
>
> But A31 IR driver is compatible with A64.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
> 1 file changed, 1 insertion(+)
>

Reviewed-by: Rob Herring <ro...@kernel.org>

[Rob Herring]

On Sat, 8 Jun 2019 01:10:57 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> There are some minor differences between A31 or A64 with H6 IR peripheral.
>
> But A31 IR driver is compatible with H6.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> Acked-by: Sean Young <se...@mess.org>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
> 1 file changed, 1 insertion(+)
>

Reviewed-by: Rob Herring <ro...@kernel.org>

[Clément Péron]

Hi Sean,

You acked the whole v3 series but this patch has been introduced in v5
could you ack this one too?

Thanks,
Clément

[Clément Péron]

Hi,

This series received ack from device-tree, media and sunxi maintainers.

Can patch 2/3/4 goes to linux-media and the rest to linux-sunxi ?

Thanks,
Clément

[Maxime Ripard]

Hi Sean,

On Tue, Jul 23, 2019 at 07:25:57AM +0100, Sean Young wrote:
> On Mon, Jul 15, 2019 at 01:12:45PM +0100, Sean Young wrote:

> > On Sun, Jul 14, 2019 at 04:32:22PM +0200, Clément Péron wrote:
> > > Hi Sean,
> > >
> > > You acked the whole v3 series but this patch has been introduced in v5
> > > could you ack this one too?
> >

> > Acked-by: Sean Young <se...@mess.org>
>
> So who's tree should this series go through? It seems mostly device tree.
> Alternatively I'm happy to try it get merged via the media tree.

Ideally the media bits should go through the media tree, the DT bits
will go through arm-soc

So you can apply the patches 1-4, 7 and 10, I'll apply the rest.

Does that work for you?

Thanks!

[Maxime Ripard]

On Wed, Jul 24, 2019 at 06:39:37AM +0100, Sean Young wrote:

> On Tue, Jul 23, 2019 at 09:04:40AM +0200, Maxime Ripard wrote:
> > Hi Sean,
> >
> > On Tue, Jul 23, 2019 at 07:25:57AM +0100, Sean Young wrote:
> > > On Mon, Jul 15, 2019 at 01:12:45PM +0100, Sean Young wrote:
> > > > On Sun, Jul 14, 2019 at 04:32:22PM +0200, Clément Péron wrote:
> > > > > Hi Sean,
> > > > >
> > > > > You acked the whole v3 series but this patch has been introduced in v5
> > > > > could you ack this one too?
> > > >
> > > > Acked-by: Sean Young <se...@mess.org>
> > >
> > > So who's tree should this series go through? It seems mostly device tree.
> > > Alternatively I'm happy to try it get merged via the media tree.
> >
> > Ideally the media bits should go through the media tree, the DT bits
> > will go through arm-soc
> >
> > So you can apply the patches 1-4, 7 and 10, I'll apply the rest.
> >
> > Does that work for you?
>

> Works for me, I'll add them to my next pull request to Mauro.

Applied 5, 6, 8, 9 and 11 to 13.

Thanks!
Maxmie