OpenHPSDR port to Xilinx ZYNQ™-7000
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Art
Feb 17, 2022, 11:16:56 PM2/17/22
to Hermes-Lite
Hello Dear Group.
I wonder if someone ported the openhpsdr protocol to the FPGA Xilinx, for example - ZYNQ 7000? Is there any project other than the Red Pitaya project?
I wonder if someone ported the openhpsdr protocol to the FPGA Xilinx, for example - ZYNQ 7000? Is there any project other than the Red Pitaya project?
"Christoph v. Wüllen"
Feb 18, 2022, 3:52:43 AM2/18/22
to Art, herme...@googlegroups.com
This is a misunderstanding.
In those "FPGA+ARM" chips, the OpenHPSDR protocol is implemented in plain vanilla C, and this is very easily done.
See the attached file (from RedPitaya). The C program directly accesses the TX and RX FIFOs in the FPGA.
Note that some other projects such as the original "Radioberry" project followed the same lines. And I personally think
this is the way to go.
In those "FPGA+ARM" chips, the OpenHPSDR protocol is implemented in plain vanilla C, and this is very easily done.
See the attached file (from RedPitaya). The C program directly accesses the TX and RX FIFOs in the FPGA.
Note that some other projects such as the original "Radioberry" project followed the same lines. And I personally think
this is the way to go.
Genadi Zawidowski
Feb 18, 2022, 1:15:00 PM2/18/22
to Hermes-Lite
Hello.
One of configurations in open source project Storch support ZYNQ70xx.
Other configurations based on Altera EP4CE22xx
Other configurations based on Altera EP4CE22xx
Art
Feb 19, 2022, 4:27:05 AM2/19/22
to Hermes-Lite
Hello group. Thanks for the information. Still, the economic situation around the FPGA from Altera forces us to look for cheaper options. Here the question is more in DSP processing.
пятница, 18 февраля 2022 г. в 20:15:00 UTC+2, mgs...@mail.ru:
DL1YCF
Feb 19, 2022, 5:41:48 AM2/19/22
to Art, herme...@googlegroups.com
I think the topic is of more general interest. I cannot make predictions about the hardware market, but
there seems to be a move from „pure FPGAS“ towards „FPGA+ARM CPU“ combinations which will force us to
re-think the FPGA programming.
In an „FPGA+ARM“ situation, the detection and processing of METIS discovery packets etc. would be done
in the CPU (the FPGA would not even know about it), the same applies to the CW keyer, all the handling
of UDP and ports, and so forth. Furthermore, all the I/O is then done by the CPU (e.g. shipping out
the (frequency dependent) i2s data for band filter switching etc. etc. etc. etc., so nearly everything
that is *not* DSP will be done by the CPU.
The actual „chip shortage“ may (from hindsight) be seen a catalyst that accelerated this transition.
So dear Altera affectionados, have a look what the RedPitaya people do, it might come over you
sooner than expected.
Yours,
Christoph DL1YCF.
> Am 19.02.2022 um 10:27 schrieb Art <cqdx...@gmail.com>:
>
> Hello group. Thanks for the information. Still, the economic situation around the FPGA from Altera forces us to look for cheaper options. Here the question is more in DSP processing.
>
> пятница, 18 февраля 2022 г. в 20:15:00 UTC+2, mgs...@mail.ru:
> Hello.
> One of configurations in open source project Storch support ZYNQ70xx.
> Other configurations based on Altera EP4CE22xx
> Next version planned on MYC-Y7Z010/20 CPU Module
>
> You received this message because you are subscribed to the Google Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/hermes-lite/3b08931b-1065-49d0-9952-9abcb50da06bn%40googlegroups.com.
there seems to be a move from „pure FPGAS“ towards „FPGA+ARM CPU“ combinations which will force us to
re-think the FPGA programming.
In an „FPGA+ARM“ situation, the detection and processing of METIS discovery packets etc. would be done
in the CPU (the FPGA would not even know about it), the same applies to the CW keyer, all the handling
of UDP and ports, and so forth. Furthermore, all the I/O is then done by the CPU (e.g. shipping out
the (frequency dependent) i2s data for band filter switching etc. etc. etc. etc., so nearly everything
that is *not* DSP will be done by the CPU.
The actual „chip shortage“ may (from hindsight) be seen a catalyst that accelerated this transition.
So dear Altera affectionados, have a look what the RedPitaya people do, it might come over you
sooner than expected.
Yours,
Christoph DL1YCF.
> Am 19.02.2022 um 10:27 schrieb Art <cqdx...@gmail.com>:
>
> Hello group. Thanks for the information. Still, the economic situation around the FPGA from Altera forces us to look for cheaper options. Here the question is more in DSP processing.
>
> пятница, 18 февраля 2022 г. в 20:15:00 UTC+2, mgs...@mail.ru:
> Hello.
> One of configurations in open source project Storch support ZYNQ70xx.
> Other configurations based on Altera EP4CE22xx
> Next version planned on MYC-Y7Z010/20 CPU Module
>
> On Friday, February 18, 2022 at 7:16:56 AM UTC+3 Art wrote:
> Hello Dear Group.
> I wonder if someone ported the openhpsdr protocol to the FPGA Xilinx, for example - ZYNQ 7000? Is there any project other than the Red Pitaya project?
>
> --
> Hello Dear Group.
> I wonder if someone ported the openhpsdr protocol to the FPGA Xilinx, for example - ZYNQ 7000? Is there any project other than the Red Pitaya project?
>
> You received this message because you are subscribed to the Google Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/hermes-lite/3b08931b-1065-49d0-9952-9abcb50da06bn%40googlegroups.com.
Larry Dodd
Feb 19, 2022, 7:24:39 AM2/19/22
to Art, Hermes-Lite
Art,
You might take a look at Panoradio SDR by DC9ST years ago.
Larry K4LED
------------
K4LED Links:
On Feb 19, 2022, at 4:27 AM, Art <cqdx...@gmail.com> wrote:
Hello group. Thanks for the information. Still, the economic situation around the FPGA from Altera forces us to look for cheaper options. Here the question is more in DSP processing.
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