Exception vector assembly code

[Angus Gratton]

I haven't linked this from the wiki, but I thought it might be of interest.

I've extracted an assembler version of the interrupt vectors & low-level handlers in the RTOS SDK 0.9.9, for esp-open-rtos. Equivalent to xtensa_vectors.o from libmain.

https://github.com/SuperHouse/esp-open-rtos/commit/ed7ba52c9acc000c8ebc250a3d4ba889261dd7ef

It's not strictly the same (for example I simplified the linkage sections), but the output is pretty close to the same.

These will probably start diverging from the RTOS SDK pretty shortly, at the very least there's some cruft I can clean up. So I thought I'd point out this version while it looks like this.


Angus

[Alex Stewart]

Neat!

Any idea what _EmptyVectorEntry and _EmptyVectorEntry2 actually are?  I have to admit I'd been digging into this part of the SDK a little bit back and getting rather confused..  The Xtensa docs on how exception vectors are actually indexed/handled are really bizarrely vague and confusing in parts..

--Alex

Angus

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[Alex Stewart]

Also, it looks like the vector table offsets for the SDK (and your equivalent code) don't actually match up with the offsets listed in http://esp8266-re.foogod.com/wiki/Memory_Map#bootrom ?  Do the vector offsets from VECBASE actually change somehow when you move VECBASE somewhere else, or is that table of default vector locations actually wrong?

--Alex

[Angus Gratton]

Hey Alex,

On Tue, Jul 28, 2015 at 03:02:27PM -0700, Alex Stewart wrote:
> Also, it looks like the vector table offsets for the SDK (and your
> equivalent code) don't actually match up with the offsets listed in
> http://esp8266-re.foogod.com/wiki/Memory_Map#bootrom ? Do the vector
> offsets from VECBASE actually change somehow when you move VECBASE
> somewhere else, or is that table of default vector locations actually wrong?

At a glance the table matches up with what I've seen/written. The vectors are in the same order, and the gaps are at 0x40 and 0x60. What was the difference you were thinking of?

The only key difference I know of is that the reset vector never gets called (AFAIK) in the IRAM-located handlers, as the core goes back to the BootROM vecbase on reset. It's probably possible to drop that entry off entirely, save 16 bytes. :)

Regarding what goes at those other offsets (0x40, 0x60), AFAIK nothing does. I think the only exception types supported by lx106 are the ones mentioned. I don't really know why the core designers included gaps, maybe to provide more space for "inline" KernelException & UserException vector code, as these are the most versatile exception types? That's just a guess though.

jcmvbkc gave a succinct explanation of how the vector offsets are laid out, here:
http://www.esp8266.com/viewtopic.php?f=9&t=3979&start=10#p23058


Angus

[Alex Stewart]

Ah, sorry, you're right.. The way the table was laid out I'd missed that there are actually gaps in the addresses there too..

According to the Xtensa ISA documentation, it sounds like the LX106 can theoretically support up to 17 different types of exception vectors depending on what chip features are configured and which are chosen to be enabled vectors by the client (Espressif), which is why I wasn't so sure that those gaps might not actually be something interesting..

--Alex

Angus

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