black box and parameters

[Martin Schoeberl]

Hi all,

is there a way to provide parameters with a black box? Something done with defparam in Verilog or generic in VHDL.

Cheers,
Martin

[Schuyler Eldridge]

Take a look at hcl.scala (https://github.com/ucb-bar/chisel/blob/master/src/main/scala/hcl.scala). For a blackbox you can establish parameters with the VerilogParameters class and then apply the parameters to the blackbox with setVerilogParameters. There's a short example in hcl.scala of how to do this.

Note, you can alternatively do this directly with setVerilogParameters, but that is really just a way to append a string after the Verilog module name. A short example of the latter is below from a generic SRAM module that I use: 

class SRAM (
  val dataWidth: Int = 8,
  val sramDepth: Int = 64
) extends BlackBox {
  setVerilogParameters(
    "#(.WIDTH(" + dataWidth + ")," +
      ".DEPTH(" + sramDepth + ")," +
      ".LG_DEPTH(" + log2Up(sramDepth) + "))\n ")
  setName("sram")
// ...
}

[Schuyler Eldridge]

Alternatively, Yaman has an example using VerilogParameters here (https://github.com/maltanar/fpga-tidbits/blob/master/on-chip-memory/DualPortBRAM.scala) which interfaces to a backend Verilog BRAM here (https://github.com/maltanar/fpga-tidbits/blob/master/on-chip-memory/DualPortBRAM.v).

[Martin Schoeberl]

Hi Schuyler,

thanks, that worked out nicely.

Cheers,
Martin

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