How can I append /*verilator public*/ to signals?
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Øyvind Harboe
Sep 25, 2020, 2:59:48 AM9/25/20
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I want some input/output signals in the Verilator model to be public members of the C++ classes, which allows me to integrate my Verilator C++ code with our test application.
The way this is achieved is by using adding /*verilator public*/ to the end of the io signal in the Verilog code, like:
The way this is achieved is by using adding /*verilator public*/ to the end of the io signal in the Verilog code, like:
io_foo /*verilator public*/,
Today I'm honering the fine tradition of using perl scripts to muck about with the Verilog, but my scripts occasionally fall over as I upgrade and the Verilog changes very subtly.
Is there a better way to add "/*verilator public*/" to the end of input/output signals of a module?
Jiuyang Liu
Sep 25, 2020, 10:12:36 AM9/25/20
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Hi, Øyvind
Verilator doesn’t support verilog attributes.
But chisel did
Hope this helps.
The verilator’s way to support attributes doesn’t so *standard*. I think we need to contribute to verilator rather than chisel to support it.
I’m not so familiar with verilator. But if I have time I may try to investigate.
Thanks,
Jiuyang
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Stefan Wallentowitz
Sep 25, 2020, 10:15:11 AM9/25/20
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Hi,
the "prefered" way (IMO) is to set them via a verilator file, which I
added earlier this year. The topic is mentioned as a side note here:
https://wallento.cs.hm.edu/post/20200612-verilator-waivers/
Best,
Stefan
the "prefered" way (IMO) is to set them via a verilator file, which I
added earlier this year. The topic is mentioned as a side note here:
https://wallento.cs.hm.edu/post/20200612-verilator-waivers/
Best,
Stefan
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Øyvind Harboe
Sep 25, 2020, 2:14:08 PM9/25/20
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The problem then becomes that I have to manually maintain this "out of bands" file, wheras, if I understand correctly, parameters are bound directly to the Chisel code. If I rename a signal I have two places to update.
I see the attraction of separating the Verilator concern from the Chisel concern though. I like that aspect.
Come to think of it... Tcl constraint files are another example of separating concerns: behavioral logic in Chisel from physical realization. A Tcl constraint file can choose how to implement a register that is changed on an enable signal: use mux with feedback, clock gating or standard cell, for instance.
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ste...@wallentowitz.de
Sep 25, 2020, 2:26:38 PM9/25/20
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Yes, you can pretty much compare it to a constraint file, I believe. The syntax allows for wildcards, which makes it flexible enough for most maintenance cases. If you believe a syntax option is missing, I am happy to extend it.
Maybe this file can be generated alongside verilog from chisel "annotations" (leaving my comfort zone here..)
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Jack Koenig
Sep 25, 2020, 2:30:09 PM9/25/20
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Stefan hit send about 30 seconds before I was about to.
As Stefan said, waiver files like this, or Tcl constraint files for physical design, can be handled via Chisel/FIRRTL annotations.
I'll try to put together a demo to show how this could work.
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Øyvind Harboe
Sep 25, 2020, 2:30:33 PM9/25/20
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Certainly Tcl constraints files are not going away anytime soon, so if Chisel can support that workflow perhaps it can work for Verilator constraint files too...
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Øyvind Harboe
Sep 25, 2020, 2:59:44 PM9/25/20
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I'll try it out on Verilator, although I'm also interested in learning this for Tcl.
Thanks!
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Øyvind Harboe
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Jiuyang Liu
Sep 25, 2020, 4:07:45 PM9/25/20
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About the tcl or other physical design problems, I think it’s more complex than expected: tcl contains should apply to netlist, while firrtl only have the information until verilog.
Sometime annotated signal can match to post synthesis signal is because synthesis tool keeps signals name successfully. However sometimes signal will become inlined, optimised, or renamed, while firrtl doesn’t have these informations, it will raise signal not found problems in this situation.
I encounter this problem in vivado, when annotate clock signal and convert them to tcl. So I think this won’t be a easy task to solve.
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Stefan Wallentowitz
Sep 26, 2020, 2:40:01 AM9/26/20
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I think there are two solutions to this problem. First, you could use
rather generous wildcards, with the drawback of false positives of a
waiver. Alternatively, all transforms should equally apply to the signal
annotations too, but with the huge issue that all transforms need to be
touched and need to know the semantics. As you say, this can be hard..
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rather generous wildcards, with the drawback of false positives of a
waiver. Alternatively, all transforms should equally apply to the signal
annotations too, but with the huge issue that all transforms need to be
touched and need to know the semantics. As you say, this can be hard..
> <mailto:oyv...@harboe.org>> wrote:
>
> The problem then becomes that I have to manually
> maintain this "out of bands" file, wheras, if I
> understand correctly, parameters are bound directly to
> the Chisel code. If I rename a signal I have two places
> to update.
>
> I see the attraction of separating the Verilator concern
> from the Chisel concern though. I like that aspect.
>
>
> Come to think of it... Tcl constraint files are another
> example of separating concerns: behavioral logic in
> Chisel from physical realization. A Tcl constraint file
> can choose how to implement a register that is changed
> on an enable signal: use mux with feedback, clock gating
> or standard cell, for instance.
>
> fre. 25. sep. 2020, 16:15 skrev Stefan Wallentowitz
> <ste...@wallentowitz.de <mailto:ste...@wallentowitz.de>>:
>
> The problem then becomes that I have to manually
> maintain this "out of bands" file, wheras, if I
> understand correctly, parameters are bound directly to
> the Chisel code. If I rename a signal I have two places
> to update.
>
> I see the attraction of separating the Verilator concern
> from the Chisel concern though. I like that aspect.
>
>
> Come to think of it... Tcl constraint files are another
> example of separating concerns: behavioral logic in
> Chisel from physical realization. A Tcl constraint file
> can choose how to implement a register that is changed
> on an enable signal: use mux with feedback, clock gating
> or standard cell, for instance.
>
> fre. 25. sep. 2020, 16:15 skrev Stefan Wallentowitz
>
>
> > <mailto:chisel-users...@googlegroups.com
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