verilator_coverage and ChiselTest

[Warren Savage]

Does anyone know whether the verilator_coverage feature works with ChiselTest?

After simulation I get a coverage.dat file with a single line:

# SystemC::Coverage-3

I'm assuming it doesn't work, because I've never seen any mention of embedding Verilator pragmas into Chisel.  But then I see the flags for it in  FIRRTL, which seems odd.

I thought I'd ask this esteemed group here in case I missed something.

Second, somewhat related question.  Is it possible to run a Verilator simulation outside of sbt?  When I run a previously generated verilated binary from the bash shell, I get a segmentation fault.

Warren

[Kevin Laeufer]

Hi Warren,

chiseltest enables "user" coverage by default to collect count for any
`cover` statements in the Chisel source code.

An example can be found here:
https://scastie.scala-lang.org/6lCoSG9PR5iHT1LlBKtJTw
This uses the default treadle backend, since Verilator is not supported
on Scastie. However, you should be able to run the same example locally
and switch the backend to use Verilator, and it should work exactly the
same.

Addressing your second question: The C++ test harness generated by
chiseltest is meant to be a JNA library that can be loaded into the JVM
to allow your Scala testbench to interact with the native simulator with
minimal overhead. Thus, you cannot execute it. You could write your own
C++ testbench. However, since all the inputs and expected outputs are
still encoded as a Scala program, you would also have to port those
manually.
There used to be an option that allowed users to export test stimuli as
a Verilog testbench. We could bring that back if there is demand or even
implementation help from the community.

Best,
Kevin

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[Warren Savage]

Thanks Kevin,

It works perfectly.

Warren

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