FIFO Interface signal naming

[Mike Butts]

When using FIFO interfaces, I like to use Ready/Valid signal names. It's so much clearer. There's an short article showing this, with very good examples:

http://inst.eecs.berkeley.edu/~cs150/Documents/Interfaces.pdf

The article says, 

- "The Valid signal (output from the source and input to the sink) indicates that the source has put valid data on the Data line this cycle. Valid is high only when data is valid. If data is not valid on the Data line during a particular cycle, Valid should be low during that cycle."

- "The Ready signal (output from the sink and input to the source) indicates that the sink is ready to receive new data. Ready can be asserted as soon as the sink is ready to receive new data. Whenever the sink is not ready to receive new data, Ready should be low."

When ready and valid are both true, data is transferred that cycle.  It's also important to stick to FIFO behavior, so once a valid or ready signal goes true, it must stay true until its data is transferred.

Ready/Valid interfaces are easy to snap together, and can transfer data every cycle.

I use wire names f2hData, f2hValid and f2hReady on comm_fpga's chanData_in, chanGotData_in and chanRead_out pins.

I use wire names h2fData, h2fValid and h2fReady on comm_fpga's chanData_out, chanWrite_out and chanGotRoom_in pins.

// Channel read/write interface:

wire[6:0]  chanAddr; // the selected channel (0-127)

wire[7:0]  f2hData; // (chanDataIn) data lines used when the host reads from a channel

wire       f2hReady; // (chanRead) '1' means "on the next clock rising edge, put your next byte of data on chanData_in"

reg        f2hValid; // (chanGotData) channel logic can drive this low to say "I don't have data ready for you"

wire[7:0]  h2fData; // (chanDataOut) data lines used when the host writes to a channel

wire       h2fValid; // (chanWrite) '1' means "on the next clock rising edge, please accept the data on chanData_out"

wire       h2fReady; // (chanGotRoom) channel logic can drive this low to say "I'm not ready for more data yet"

comm_fpga fx2if (.fx2Clk_in(fx2Clk_in), .fx2FifoSel_out(fx2Addr_out[0]), .fx2Data_io(fx2Data_io),

.fx2Read_out(fx2Read), .fx2GotData_in(fx2GotData_in), .fx2Write_out(fx2Write_out),

.fx2GotRoom_in(fx2GotRoom_in), .fx2PktEnd_out(fx2PktEnd_out), 

.chanAddr_out(chanAddr), .chanData_in(f2hData), .chanRead_out(f2hReady), .chanGotData_in(f2hValid),

.chanData_out(h2fData), .chanWrite_out(h2fValid), .chanGotRoom_in(h2fReady));

  --Mike

[Chris McClelland]

I'm tempted to adopt this nomenclature. I have difficulty understanding
the interface without the _in and _out suffixes, but I guess the f2h and
h2f prefixes and the Data/Read/Valid convention does make more sense
from a system-design point of view.

Does anyone else have any strong feelings (pro or con) about this?

Chris

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