always @(posedge clk or negedge rstn) begin
if (!rstn) beginreset opsend elseif (smt) beginmain opsend
end
always @(posedge clk) begin
if (reset) beginreset opsendif (smt) beginmain opsend
end
Hi Chris,
This is indeed an interesting solution. This implies adapting the Verilog backend accordingly of course (also true for the chisel tester related code).
Unfortunately VHDL does not provide macros as suggested in the blog. For my VHDL backend I’d need to use generate statements or better pass a backend specific parameter to the code generator.
Anyway, I think it would make sense to have a solution compatible to all backend if the feature is of common interest.
Regards,
Stephan
I absolutely agree! Even so one might personally prefer asynchronous to synchronous resets or vice versa there is usually I very simple acceptance criteria within companies: Design rule! It is obvious that such an option can break things when used on arbitrary chisel based designs! Since I am currently working on a VHDL backend I tend to add a global option to the code generator as it seems easier to me than having custom scripts for conversion.