SiFive core / StarFive SoC documentation

[Daniel Maslowski]

Hey everyone,

I've asked for SoC documentation in https://groups.google.com/a/riscv.org/g/devboard-community/c/6bRddj9Gqhg - though that's a bit hard to find, so let's start a new thread.

While working on an oreboot port for the VisionFive 1, I've been struggling with the existing documentation ( https://doc-en.rvspace.org/JH7100/PDF/JH7100%20Datasheet.pdf ) that refers to existing code instead of having register MMIO addresses, trying to find a full SoC manual for the JH7100. Selina from StarFive said that peripherals such as the DRAM controller are not open / NDA only, and pointed to this PDF for the actual core:

https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf

I'll verify whether 21G3 is indeed what we get from reading the registers.

Now it would be best to have an SVD file (see ARM CMSIS-SVD https://www.keil.com/pack/doc/CMSIS/SVD/html/index.html ), from which we could generate a Rust crate,  C/C++ header files etc, to talk directly to all of the hardware, assist with debugging (including JTAG + gdb). I have found this here, which does not include the U74, but the older FU540 core:

https://github.com/sifive/cmsis-svd-generator/tree/master/regmaps

It's backwards in that it generates SVDs based on DTS files, which someone would need to write first. Only a subset exists in the Linux port, omitting what we would need for the silicon init in firmware. But it's a start. :-)

I will document register semantics in oreboot if I can figure things out. If anyone would like to contribute or could benefit from SVDs otherwise, please do let me know so that we can see that we work something out.

Hope this helps to get an overview and understanding.

Regards

Daniel

[Daniel Maslowski]

For further reference, here is the U-Boot DTS for the JH7100 / VisionFive 1:

https://github.com/starfive-tech/u-boot/blob/07eac31890155be6005237cecdc1871d471c86c7/arch/riscv/dts/jh7100-visionfive.dts

I couldn't get this processed with SiFive's cmsis-svd-generator yet, even after preprocessing and flattening. Will post further results.

Gist with the corresponding scripts:

https://gist.github.com/orangecms/2d014eb3a21123b4da89d13f974f7c6b

To preprocess (script in Gist):

dts-preprocess.sh arch/riscv/dts/jh7100-visionfive.dts

Run through cmsis-svd-generator:

mkdir svd-test; cd svd-test

git clone https://github.com/sifive/pydevicetree

git clone https://github.com/sifive/cmsis-svd-generator

cd cmsis-svd-generator

PYTHONPATH=(pwd)/../pydevicetree ./generate_svd.py -d /tmp/resolved.dts -o jh7100-visionfive.svd

Will yield errors in parsing, unfortunately; not sure yet why.

And here's a blog post with an SVD example:

https://www.cnblogs.com/qiyuexin/p/12896365.html

[Daniel Maslowski]

Here is the corresponding issue: https://github.com/sifive/cmsis-svd-generator/issues/16

If anyone is more familiar with Python and parser shenanigans, help would be appreciated. :)