Good news. Teases of JH-7110 appear

[Robert Lipe]

We've known for over a year that the JH-7100 that's used in VisionFive and before that, Beagle, was a bit of a sitting duck. Last spring, StarFive was vigorously closing bugreports as things were known in the (then considered to be limited run/temporary) 7100 and fixed in the successor, the JH-7110 but it's been a long time since we'd seen any progress publicly.

Last month, Pine64 teased a new board, but today they announced that Star64 will have the JH-7110.

JH-7110 is still using the four year old (sigh) U74 cores from SiFive and thus won't have Vector support or, likely, most of the newer specs. This does unlock all four cores (yay!) and bumps the clock from 1 to 1.5Ghz. It has an inbuilt GPU and has a PCIe slot so you can presumably add another. The part SHOULD fix the errata, like the DMA "inconvenience" that required manual shootdown of pages that were modified by dirty pages, bringing it back to the RISC-V guidance of not building designs that require manual bus synchronization operations. 

I haven't seen the datasheets on the 7110 yet, but I have expectations that our work on VisionFive should come forward with a high degree of compatibility.  Sure, video will need work and things like the DMA coherency patches will need some tweaking to be disabled on the newer chips, but I'd expect that most things will work with minor-ish kernel-level work. The cores are still U74MCs so the compiler-level stuff should be unchanged.

I'm pretty chuffed as this should be one of our first real contenders at a usable desktoppy device. 8GB is enough to actually be usable in your favorite OS without chopping it down terribly. 3D video is table stakes for many users. The board will be more than the Pi's theoretical $35 price, but way under the $667 of the unobtainable SiFive boards. D1's smaller configuration (single core, Allwinner-isms) will have a place at the low end, but I'm pretty happy to see this hole in the RISC-V product space filled.

https://www.hackster.io/news/pine64-formally-unveils-the-starfive-jh7110-powered-star64-risc-v-single-board-computer-3917fae60eb9

[Jeff Scheel]

Nice!  Thanks for sharing!!!

-Jeff

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Jeff Scheel (he/him/his)

Linux Foundation, RISC-V Technical Program Manager

[ge...@codingpanic.com]

Yes, I read the same! This looks exciting. 

I wonder if this fixes some of the performance issues when using USB3.0 ports and Ethernet at the same time (I think its related to the L2 cache coherence problem on the JH7100)

Also, a “real” graphics core is a welcome change!

Exciting times...

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[Robert Lipe]

On Mon, Aug 1, 2022 at 11:39 AM Daniel Maslowski <cyre...@googlemail.com> wrote:

Are there any traces of SoC or core documentation?

Not that I've seen. It'll still be the U74MC core complex, "just" with a GPU bolted on and a PCIe slot.

 

So far, I am stuck with the JH7100, and the best I could do would be to reverse engineer the existing messy C code, which writes arbitrary bytes to arbitrary addresses in many places, i.e., is not really open.

The 7100 doc is quite complete. I'm not sure what you're having to reverse engineer, but we're likely holding different pieces of this elephant. 

If anyone is in contact with StarFive and/or SiFive, it'd be great if you could get them to publish their docs. Thanks!

They seem to be really good (as opposed to some vendors represented on this list - and in another window, I'm ealing with another RISC-V chip maker that's also made a mess, but isn't represented here) about providing doc and code and getting it upstreamed when the time is right and not making a giant mess of things in the process.

 We'll see.

Exciting times.
RJL

[Daniel Maslowski]

Are there any traces of SoC or core documentation?

So far, I am stuck with the JH7100, and the best I could do would be to reverse engineer the existing messy C code, which writes arbitrary bytes to arbitrary addresses in many places, i.e., is not really open.

Trying to get behind that, as we all know, takes a lot of time and easily ends up in false conclusions or remaining unknowns. With that low an ROI, motivation drops. I'm not calling that a great experience so far.

If anyone is in contact with StarFive and/or SiFive, it'd be great if you could get them to publish their docs. Thanks!

[Jeff Scheel]

On Tue, Aug 2, 2022 at 8:20 AM 'Daniel Maslowski' via RISC-V Developer Board Community <devboard-...@riscv.org> wrote:

Are there any traces of SoC or core documentation?

So far, I am stuck with the JH7100, and the best I could do would be to reverse engineer the existing messy C code, which writes arbitrary bytes to arbitrary addresses in many places, i.e., is not really open.

Trying to get behind that, as we all know, takes a lot of time and easily ends up in false conclusions or remaining unknowns. With that low an ROI, motivation drops. I'm not calling that a great experience so far.

If anyone is in contact with StarFive and/or SiFive, it'd be great if you could get them to publish their docs. Thanks!

Daniel,

If you'll direct mail me your more details about the documentation you need and the rationale for requesting it, I'll be more than happy to make an introduction to my contacts at StarFive.  While I cannot commit to getting the information, like Robert I have found them to be easy to work with.

[Daniel Maslowski]

Hi Jeff,

Thank you, that sounds great! :) Here is a list of information we need:

## RISC-V Core Manual

We were unsure which of the various U7, U74, U74-MC etc is what's in the JH7100. There are documents starting with VIC in the JH7100_Docs repository.
Is this https://github.com/starfive-tech/JH7100_Docs/blob/main/vic_u7_manual_with_creativecommons.pdf the correct manual for the two cores found in the JH7100?

## JTAG Debugging

Setting up a debugger is very useful for development. This is what we have figured out over time, which would be great to have documentation on: https://forum.rvspace.org/t/connecting-to-visionfive-s-jtag-port-a-short-guide/514

Could we have a comprehensive manual for JTAG setup with OpenOCD and GDB?

## SysCon, GPIOs, Configuration

There are various register definitions in the JH7100_secondBoot etc source code. We are searching for documentation on those, e.g., to configure the GPIO pins. For example, this is what we figured out would move the UART to other pins:
_SET_SYSCON_REG_register104_SCFG_io_padshare_sel(6);
( https://github.com/starfive-tech/JH7100_secondBoot/blob/e17302063c9a4b74475b18ff24dd149c27257354/boot/bootmain.c#L178-L183 )

The data sheet ( https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf ) lists the peripherals and memory map plus the matrix with IO pad functionality.

It refers to `IO_PADSHARE_SEL`, which can be found in the Linux source code, too, so we could take the address from there. Grepping through multiple repositories to figure things out is rather tedious, though.

Where can we find documentation on the peripherals themselves, how they work in general, and the control and status registers?

## DRAM

Having documentation on the DRAM controller would be a great plus. As per the JH7100 docs, it is an OpenEdges OMC (ORBIT Memory Controller). There is a product brief: https://www.openedges.com/memorycontroller

It would be great to have the registers and setup flow documented and what they mean/do. Then we could adapt and document the code for comprehensibility, and potentially reuse the knowledge for further ports and boards.

As a benchmark comparison, for the Allwinner D1 SoC we had an assembly dump with rough function names, which had been translated to C, and I then ported to Rust.

We got to the point where we boot from power-on into a full LinuxBoot environment within 5 seconds. It would be very beneficial to get to the same level with the JH7100.

## How to provide documentation

In the oreboot project, we have a repository where documents can be added: https://github.com/oreboot/datasheets

Additionally, the Rust ecosystem features so-called PACs (peripheral access crates), which reflect the documentation of hardware, its registers, peripherals, etc..

Those can be generated from SVD files, which are machine-processable hardware descriptions.

Thank you again very kindly.

Daniel

[Zheng Selina]

Hi Daniel,

Question 1: JH7100 uses U74 cores. So I think the U74 Manual could be a good source for you. 

The difference about U7: U7 is the 7 series core with MMU; U74 is the only core currently in SiFive 7 series; U74-MC is a cluster with multi-cores, including 4 U7 and 1 S7. If you want the core manual, you could go to SiFive website and search for U74 core manual: https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf

Question 2: JTAG is developed by several community developers. And then they showed their work in RVspace forum. If you are interested I could help you make an introduction to these developers.

Question 3 and 4: Our public documentation for GPIO is in the following link (https://rvspace.org/en/Product/General/StarFive_40-Pin_GPIO_Header_User_Guide). For other documentation, due to our contract with our vendors, we could not publish their IP information without their official approval. We could try to connect you with the corresponding vendor to see if they are willing to show you the documentation.

Best,

Selina

[Dusten Sobotta]

Exciting times! I'm very happy to see good rust support forming around these devices, and the esp32c3 too!

[Daniel Maslowski]

Hi Selina,

1: I am still confused, sorry. Maybe even more so now.

2: That is what I referenced above and it would really help if you (StarFive) would provide documentation instead of having people figure things out. That holds back your customers and is being hostile to the wider community, not good for reputation. I am sorry to phrase it this way..

3+4: Again, that is what I referenced, and it isn't helpful. Please reach out to the peripheral providers for documentation and document your SoCs fully. There is currently no information on the upcoming JH7110 either. That is necessary for firmware work. Please note that you will largely benefit from an expert community that had been writing firmware for decades. We are looking forward to bringing our knowledge to your products.

As to what Dusten Sobotta writes:

Yes, we are very happy to see good Rust support. So far it does not exist from StarFive and the only bits we have stem from community efforts and reverse engineering. We are looking forward to more vendor support, like Espressif already does it with their excellent Rust crates and even toolchain port.

Please provide the SVD files and the corresponding full SoC manuals to make this a reality, Selina / StarFive. Thank you!

Regards

Daniel

[Jeff Scheel]

Hi, Daniel, thanks for your response to Selina's reply.  In an effort to keep this discussion productive, I'm going to ask some questions and make some comments.

1: I am still confused, sorry. Maybe even more so now.

My understanding of what Selina is saying is that  SiFive has more documentation (her link) about the core (U74)  than what StarFive provides (your original link).  Is there a specific question you are trying to answer with the core documentation?  If so, perhaps posing it would help us find the "proper" documentation.

2: That is what I referenced above and it would really help if you (StarFive) would provide documentation instead of having people figure things out. That holds back your customers and is being hostile to the wider community, not good for reputation. I am sorry to phrase it this way..

3+4: Again, that is what I referenced, and it isn't helpful. Please reach out to the peripheral providers for documentation and document your SoCs fully. There is currently no information on the upcoming JH7110 either. That is necessary for firmware work. Please note that you will largely benefit from an expert community that had been writing firmware for decades. We are looking forward to bringing our knowledge to your products.

While I understand your frustration, I can also understand StarFive's situation where they've purchased IP for the SOC and that base agreement doesn't allow them to share the documentation from the IP vendor.  While they could have perhaps negotiated that release while negotiating the contract, this can make complex decisions even harder.  (Been there, done that.)  The way this cycle changes, in my opinion, is for the original IP vendors to understand the value that OSS communities can provide with proper documentation.  As such, I'd strongly recommend that we use Selina's offer to reach out to them.  This way, the original IP vendors get the request directly.  The worse that happens from those discussions is that they have a greater understanding of the needs of OSS communities for documentation.  This can bear fruit in the future.

How does this sound?  Can we try my approach in hopes of taking small steps, if only through education?

-Jeff

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Jeff Scheel (he/him/his)

Linux Foundation, RISC-V Technical Program Manager

[Jeff Scheel]

Daniel, as I think about this more, I'd be willing to host the discussions with the various vendors if that would be helpful.  Then, we could invite others to attend as they feel compelled to participate.  What would you think about this idea?

Selina, would you be willing to approach the vendors about individual discussions with us?  How would we handle any language differences?

Thanks,

-Jeff

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Jeff Scheel (he/him/his)

Linux Foundation, RISC-V Technical Program Manager

[Daniel Maslowski]

Thank you Jeff,

I also needed a while to reflect on this. I think whatever brings us forward is a good step, and I'm willing to invest the time.