This is a suggestion I have made before but perhaps useful to the various correspondents and readers. When an email thread on one topic (for example, FP estimate functions locations) is re-used for a different topic (for example, code of conduct discussions), I would suggest that the subject line be changed, perhaps along the lines of what I did above.
For example, this new discussion could use as subject “Code of Conduct Discussion (Was: RE: [isa-dev] FP estimate functions location)”, for example.
In this way, those interested in the FP estimate functions discussion would know that a new thread has been created on a different topic, and they can decide if they want to follow the new topic or not.
This would help all readers, especially if using a threaded email reader.
Thanks for your consideration
Grant
-------------------------------------------------------
Grant Martin Distinguished Engineer
Tensilica R&D Cadence Design Systems
2655 Seely Avenue, Bldg#8, San Jose
CA 95134 USA Phone +1-408-944-7826
Mobile +1-510-703-7470
email gma...@cadence.com
From: lkcl <luke.l...@gmail.com>
Sent: Thursday, July 18, 2019 3:51 AM
To: RISC-V ISA Dev <isa...@groups.riscv.org>
Cc: luke.l...@gmail.com; robf...@gmail.com; con...@riscv.org; je...@linuxfoundation.org
Subject: Re: [isa-dev] FP estimate functions location
EXTERNAL MAIL
On Thu, Jul 18, 2019 at 9:52 AM Christian Brunschen <chri...@brunschen.com> wrote:
……………………
(contents removed as not needed for Grant Martin suggestion
This is a suggestion I have made before but perhaps useful to the various correspondents and readers. When an email thread on one topic (for example, FP estimate functions locations) is re-used for a different topic (for example, code of conduct discussions), I would suggest that the subject line be changed, perhaps along the lines of what I did above.
> i think also, though, that morale is pretty low right now. over the years (long before i joined) several people (and several entire teams) had already given up entirely of ever being considered as contributors to the RISC-V community, and it's kinda hard to face why that is, y'know?
I'm sorry you and the unknown others you refer to feel that way Luke.
From where I stand what I see is people who are *pumped* by the
progress RISC-V is making, whether it's the first silicon from the
Shakti team, lowRISC getting funding and hiring people, RISC-V being
accepted as an official backend in LLVM and being officially supported
in musl (both of those in the last week), or the constant stream of
new cores, new design wins, new investors, new companies being
announced on a monthly basis.
The RISC-V Vector spec seems to be causing a lot of excitement. I've
pointed it out to a few people who have done a lot of HPC or
SSE/AVX/NEON work but don't know much (or anything) about RISC-V and
they are like "Wow! When can I get this?"
Other extension groups are making good progress too, with
BitManipulation being the one I'm the most familiar with.
There are a
lot of papers coming through where people are basing academic research
around RISC-V, especially in the security area.
Multiple competitors with other ISAs have stopped ignoring RISC-V and
are changing their pricing structures and licensing to more closely
match what RISC-V vendors are doing. This benefits everyone in the
digital electronics industry and their customers, whether they are
currently using RISC-V or not.
Most of the frustration I see is just that potential customers want
RISC-V Raspberry Pi competitor boards, or phones or notebooks, or
chips for sale at mouser or digikey now now now,
not next year or the
year after or in five years. Everyone is working flat out to make that
stuff happen.
Morale low? The opposite, I would say.
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Luke,yes we were pretty annoyed at the compressed instruction decision. but was one issue way, way back when the foundation was in its infancy. two points1. please do not blow that one incident out of proportion2. if we have issues with the foundation, you can be rest assured that i will be creating a ruckus! we really do not need anyone speaking on our behalf.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAPb2fE_69D-%2BBSTg2Ng06Jj8GtwhWXQ3351ProNiOBT%3Dt%2B8rvQ%40mail.gmail.com.
As a member of the SHAKTI team, I would like to clear up quite a bit of mis-information in your last mail:
- Our SDK supports all currently ratified extensions.
- India's Processor Program is far ahead than what you seem to think. If anything, we would thank Krste (and team) for all his effort in introducing RISC-V.
- Our concerns with the foundation have been resolved back then in much mature fashion. If we do have concerns, we will continue to raise them to the respective authorities directly.
To iterate what Madhu said, we are not looking for any white-knights for us.
I would request you to consult us in future before making any claims about SHAKTI.
I had asked a question about why riscv has no instruction like MTHC in MIPS.
So the issue below is the one I understand and care about.
* a russian programmer who came up with a brilliant idea of using one of the RV64 FP opcodes to load 32-bits into the "HI" word of an RV32G (yes, G, not F, yes RV32, not RV64) 64-bit FP register (yes, 32-bit INT regfile, yes, *64* bit FP regfile). i pointed out that his idea would actually be just as applicable to solve a similar issue for RV64Q, by utilising an analogous RV128 opcode
The russian programmer is Dmitri.
This is responded in github manual issue301
https://github.com/riscv/riscv-isa-manual/pull/301
Solution and suggestion are all in the thread, but I don't know when will it bring up again and add to new spec.
Happy to see we are back to tech discusdion.
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Just dig out original discussion, first proposal from Dmitri Pavlov.For a record and reference link.https://groups.google.com/a/groups.riscv.org/forum/m/#!topic/isa-dev/kXgfFqgBv-c