To reinforce Allen's point: I have a chapter in a book on computer architecture
called pipelining. In this chapter I present a single data path of classic Stanford
RISC, and show how it can be pipelined into different implementations 7 different
ways. In all cases, it remained a 1-wide in order Scalar pipelined processor.
Now imagine doing a CDC Scoreboard version
Then Imagine doing a Tomasulo version
Then imagine 2-wide SuperScalar, 3-wide Superscalar
Then imagene a trace cache front end
Then imagine a vector back end
All of the above are orthogonal vectors of implementation.
Then, perhaps, you can see why one diagram is utterly useless in describing
some architecture which can be implemented in as many ways as you and your
brother can think.
Mitch