RISCV64 SoC Architecture diagram

153 views
Skip to first unread message

Pintu Agarwal

unread,
Nov 22, 2018, 2:34:16 AM11/22/18
to isa...@groups.riscv.org, linux...@lists.infradead.org, sw-...@groups.riscv.org, Gurucharan Kaur Saluja
Hi All,

For the education purpose, we need RISCV SoC internal architecture
diagram which can give a pictorial overview of RISCV internals.
As part of study, we want to compare this with ARMv8 architecture.

If anybody have it please share.

Also, if anybody have risv64 benchmarking data with arm64, please
share this as well.


Thanks,
Pintu

Bruce Hoult

unread,
Nov 22, 2018, 4:22:04 AM11/22/18
to Pintu Kumar, isa...@groups.riscv.org, linux...@lists.infradead.org, sw-...@groups.riscv.org, Gurucharan Kaur Saluja
RISC-V is an instruction set. It can be implemented by many different internal architectures. SiFive alone currently has three different microarchitectures that can each support 32 or 64 bit RISC-V with varying area vs performance trade-offs. Other organisations and individuals have developed many more.

The same applies to ARMv8. ARM themselves have I think nearly half a dozen different ARMv8 microarchitectures now, plus there are other independent implementations from Apple, Samsung, Qualcomm, NVidia, Cavium and probably others I can't think of now.

So, the question is meaningless.

You might want to compare some specific RISC-V design against some specific ARMv8 design. For example the SiFive U74 against the ARM A53 or A55,

You can see some (3rd party curated) information about these at:





--
You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org.
To post to this group, send email to sw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/sw-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAOuPNLiQWiqwkhKXyKV08mWz-Zfis8O3dHB0W5UVfroLU%3DW4Rw%40mail.gmail.com.

MitchAlsup

unread,
Nov 25, 2018, 7:07:18 PM11/25/18
to RISC-V ISA Dev, linux...@lists.infradead.org, sw-...@groups.riscv.org, gurucha...@gmail.com
To reinforce Allen's point: I have a chapter in a book on computer architecture 
called pipelining. In this chapter I present a single data path of classic Stanford
RISC, and show how it can be pipelined into different implementations 7 different
ways. In all cases, it remained a 1-wide in order Scalar pipelined processor.

Now imagine doing a CDC Scoreboard version
Then Imagine doing a Tomasulo version
Then imagine 2-wide SuperScalar, 3-wide Superscalar
Then imagene a trace cache front end
Then imagine a vector back end

All of the above are orthogonal vectors of implementation.

Then, perhaps, you can see why one diagram is utterly useless in describing
some architecture which can be implemented in as many ways as you and your 
brother can think.

Mitch

Reply all
Reply to author
Forward
0 new messages