RISCV64 SoC Architecture diagram

[Pintu Agarwal]

Hi All,

For the education purpose, we need RISCV SoC internal architecture
diagram which can give a pictorial overview of RISCV internals.
As part of study, we want to compare this with ARMv8 architecture.

If anybody have it please share.

Also, if anybody have risv64 benchmarking data with arm64, please
share this as well.


Thanks,
Pintu

[Bruce Hoult]

RISC-V is an instruction set. It can be implemented by many different internal architectures. SiFive alone currently has three different microarchitectures that can each support 32 or 64 bit RISC-V with varying area vs performance trade-offs. Other organisations and individuals have developed many more.

The same applies to ARMv8. ARM themselves have I think nearly half a dozen different ARMv8 microarchitectures now, plus there are other independent implementations from Apple, Samsung, Qualcomm, NVidia, Cavium and probably others I can't think of now.

So, the question is meaningless.

You might want to compare some specific RISC-V design against some specific ARMv8 design. For example the SiFive U74 against the ARM A53 or A55,

You can see some (3rd party curated) information about these at:

https://en.wikichip.org/wiki/sifive/microarchitectures/7_series

https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a53

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