Why is it required to increment PC by 4bits in RISC Architecture?

[Meet Sangani]

Hello Everyone,

I am currently working on developing a 32bit RISC-V core and I am getting confused when PC is incremented by 4 bits. Since my PC is 32bit wide so one complete instruction can be fetched from memory in one clock cycle. Then why it is required to increment PC by 4bits?

Please help me in this situation and explain in detail is possible.

[Ahmed Juba]

Hello There,

Because the memory is byte-aligned, and the instruction is 32-bits wide which's 4 bytes so in order to fetch the next instruction you have to increment the pc with 4 bytes that addresses next instruction.

[Tommy Murphy]

> and the instruction is 32-bits

Not necessarily - e.g. 16-bit compressed instructions.

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From: Ahmed Juba <ahmed.j...@gmail.com>
Sent: Thursday, February 29, 2024 2:27:27 PM
To: RISC-V HW Dev <hw-...@groups.riscv.org>
Cc: meetsanga...@gmail.com <meetsanga...@gmail.com>
Subject: [hw-dev] Re: Why is it required to increment PC by 4bits in RISC Architecture?

 

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[Tommy Murphy]

The same question was asked here:

* https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/4qEV5GmDPvc