Why is it required to increment PC by 4bits in RISC Architecture?

[Meet Sangani]

Hello Everyone,

I am currently working on developing a 32bit RISC-V core and I am getting confused when PC is incremented by 4 bits. Since my PC is 32bit wide so one complete instruction can be fetched from memory in one clock cycle. Then why it is required to increment PC by 4bits?

Please help me in this situation and explain in detail is possible.

[Richard Herveille]

PC contains byte addresses

You fetch 32bits; i.e. 4 bytes.

Hence PC must increment by 4

 

Richard

 

 

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[Tommy Murphy]

On Wednesday 20 December 2023 at 16:56:21 UTC Meet Sangani wrote:

... why it is required to increment PC by 4bits?

 

What requirement are you referring to and where is it stated?

Are you referring to some specific RISC-V implementation perhaps?

Isn't the handling of PC increments a micro-architectural issue/implementation detail outside the scope of the ISA specs?

I can't see anything in the specs that dictate how this is required to be done.