debugger

[Gnanasekar R]

Any good debuggers for RISCV that someone can suggest? I am also evaluating what might be a good feature to have in a debugger based on what RISCV debug architecture provides too. Any pointers would help.

[Tommy Murphy]

I don't think that there's anything other than the SiFive RISC-V draft debug spec, OpenOCD and gdb right now?
See here

https://www.sifive.com/documentation/risc-v/risc-v-external-debug-support/
https://github.com/riscv

Hope this helps.

[SEGGER - Alex Gruener]

Hi,

Well, there is also a solution from SEGGER with J-Link + GDBServer:
https://wiki.segger.com/SiFive_Arty_FPGA_Dev_Kit


Best regards
Alex

[Tommy Murphy]

Apologies Alex.
I thought that jlink only worked via OpenOCD and was not aware that a separate gdbserver existed for it already.
I stand corrected. :-)

[Gnanasekar R]

Hi,

Does SEGGER have support to do Real time analysis of RISC processor. Basically does SystemView work fine for a RISC target?

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[SEGGER - Alex Gruener]

Hi,

We do have support for RTT in theory.
there was no RISC-V FPGA stream so far that supports "background memory access" without halting the core.
What we did for RISC-V implementations that do not support background memory access (all so far):
RTT stop mode.
https://wiki.segger.com/RTT#Modes

There has no SystemView port for RISC-V been done so far, but by filling in the macros in the RTT target code accordingly, it should already work with SystemView.
RTT stop mode has been successfully tested with RTTViewer on RISC-V.


Best regards
Alex

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