System Bus Access

[Deepak Panwar]

Hi,

We are implementing system bus as part of debug for our RISC-V core. It's not obvious to me from the spec about what will trigger the system bus access. It's seems like writing to the "sbcs" register should trigger the access but it's not explicitly mentioned. Also, since this is also control/status register as well and we might need to update some of those status/control bits without starting a new access. Also, the debugger might want to clear the sberror bits which shouldn't start a bus access. Can someone please clarify exactly when the access will start?

Thanks,

Deepak Panwar

[Tim Newsome]

Depending on the configuration of sbcs (sbreadonaddr, sbreadondata), accesses to sbaddress0 and sbdata0 will trigger system bus accesses. The Debugger Implementation appendix contains short scan examples on how to read/write memory using the system bus, which hopefully makes it clear when exactly accesses are triggered.

Tim

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