Read memory mapped peripheral through OpenOCD

[Ânderson Ignacio da Silva]

Hello guys,

Does anybody know if is it possible to access a memory mapped peripheral through the bus memory map (in my case amba ahbv3) with OpenOCD commands in RISC-V debug transport module? I'm using the SiFive E31 IP Core complex but the datasheets does not make clear how to integrate this with the debug module. Also with the spec v.0.13 which possibilites we have available for RISC-V about hardware trace until this moment? Thanks and sorry if I committed misunderstandings...

[Tommy Murphy]

Not really sure what you mean but if the peripheral is memory mapped then you can read/write the memory mapped registers using OpenOCD's memory read/write commands (e.g. made/mww etc.) or via gdb memory commands etc. like any other part of the implemented memory map.

[Ânderson Ignacio da Silva]

Thanks for the answer Tommy, but read those registers is it possible without use hart to deal with? I mean, the commands send through openOCD makes the debug unit hardware read the bus or the processor needs to stop everything to read it....?

[Tommy Murphy]

On Friday, 5 October 2018 13:18:36 UTC+1, Ânderson Ignacio da Silva wrote:

Thanks for the answer Tommy, but read those registers is it possible without use hart to deal with? I mean, the commands send through openOCD makes the debug unit hardware read the bus or the processor needs to stop everything to read it....?

I *think* that the core/hart needs to be in debug halt for openocd and the debug module to be able to read/write memory (including memory mapped peripheral registers/memory regions). 

[Tim Newsome]

The debug spec contains 3 mechanisms to read memory:

1. Using the Program Buffer. This requires halting the hart.

2. Using the System Bus block. This can happen any time.

3. Using the abstract memory access commands. It's implementation-specific whether this can happen when running or not.

OpenOCD implements #1 and #2, but I don't think it will ever try to access memory while the hart is running, due to target-independent code inside OpenOCD.

In addition, #1 could be sped up using the Quick Access mechanism that's in the debug spec but AFAIK not implemented anywhere.

Tim

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[Ânderson Ignacio da Silva]

Hello Tim, thanks for the quick answer, so as #1 program buffer option it's not implemented yet, do you think that the best approach #2, will be halt the hart and then use mdw, mdh, mdb...to read a peripheral memory right? I'm asking those things because I want to make a cheaper trace hardware unit for the core...

[Tim Newsome]

On Fri, Oct 5, 2018 at 2:12 PM Ânderson Ignacio da Silva anders...@gmail.com wrote:

Hello Tim, thanks for the quick answer, so as #1 program buffer option it's not implemented yet, do you think that the best approach #2, will be halt the hart and then use mdw, mdh, mdb...to read a peripheral memory right? I'm asking those things because I want to make a cheaper trace hardware unit for the core...

System Bus Block is a good option for providing memory access without halting the hart. I’m not sure what you mean by mdw, mdh, mdb etc.

Tim

Em sexta-feira, 5 de outubro de 2018 17:11:57 UTC-3, Tim Newsome escreveu:

The debug spec contains 3 mechanisms to read memory:

1. Using the Program Buffer. This requires halting the hart.

2. Using the System Bus block. This can happen any time.

3. Using the abstract memory access commands. It's implementation-specific whether this can happen when running or not.

OpenOCD implements #1 and #2, but I don't think it will ever try to access memory while the hart is running, due to target-independent code inside OpenOCD.

In addition, #1 could be sped up using the Quick Access mechanism that's in the debug spec but AFAIK not implemented anywhere.

Tim

On Fri, Oct 5, 2018 at 6:06 AM Tommy Murphy <tommy_...@hotmail.com> wrote:

On Friday, 5 October 2018 13:18:36 UTC+1, Ânderson Ignacio da Silva wrote:

Thanks for the answer Tommy, but read those registers is it possible without use hart to deal with? I mean, the commands send through openOCD makes the debug unit hardware read the bus or the processor needs to stop everything to read it....?

I *think* that the core/hart needs to be in debug halt for openocd and the debug module to be able to read/write memory (including memory mapped peripheral registers/memory regions). 

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[Tommy Murphy]

mdw/mdh/mdb are the openocd commands for reading (memory dump ...) 32/16/8 bits of memory. Complemented my the mww/mwh/mwb commands for writing.

[Tim Newsome]

Thanks, Tommy.

Ânderson, once the hart is halted you can use whatever commands you like to read memory. OpenOCD will use either the Program Buffer or system bus access.

Tim

[Ânderson Ignacio da Silva]

Hello Tim and Tommy,

Thanks for the answers, I'll try test it in coreplexip e31.