Simultaneous non-chained matching triggers with different timing

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Joe Rahmeh

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Jul 3, 2018, 5:54:01 PM7/3/18
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What happens if multiple non-chained triggers match for some instruction?  Do they all trip (hit bit set to 1 for all of them)? Or, is it the case that only the "before" triggers trip and the "after" triggers do not.

Tim Newsome

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Jul 5, 2018, 11:41:02 PM7/5/18
to Joe Rahmeh, RISC-V Debug Group
The spec doesn't say, but probably should. Ideally only the "before" triggers trip but the "after" do not. An ideal core would allow a "before" trigger on a load address and also an "after" trigger on load data. In that case if the "before" trigger fires, you want to give the user control before the load happens, so the "after" check cannot be performed. But I'm not sure if that matters to other kinds of before/after trigger combinations. I'm happy to call this implementation-dependent as well. We already suggest the above timing for data load triggers. I don't think we gain anything by putting additional requirements on before/after.

What do you think?

Tim

On Tue, Jul 3, 2018 at 2:54 PM, Joe Rahmeh <joe.r...@gmail.com> wrote:
What happens if multiple non-chained triggers match for some instruction?  Do they all trip (hit bit set to 1 for all of them)? Or, is it the case that only the "before" triggers trip and the "after" triggers do not.

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