haltsum0

[Deepak Panwar]

Can someone clarify is "Halt Summary 0 (haltsum0 at 0x40)" is an optional register? We have a single thread machine so we don't see the need to implement haltsum0 since dmstatus will indicate whether the thread is halted or not. However, this is a read-only register so Debugger can't figure out it's implemented by writing to it. 

Thanks,

Deepak 

[Tommy Murphy]

On Thursday, 4 October 2018 20:32:30 UTC+1, Deepak Panwar wrote:

is "Halt Summary 0 (haltsum0 at 0x40)" is an optional register? 

Where are you seeing this register documented?

I can't see it in any of the current ISA, privileged draft or debug (v0.13) draft specs. 

[Tommy Murphy]

Sorry - I see the haltsum0 register in the draft debug spec here now:

file:///C:/Users/tommy.murphy/Downloads/riscv-debug-draft.pdf

I was unable to find the spec online earlier:

https://github.com/riscv/riscv-debug-spec/issues/386

[Tim Newsome]

haltsum0 is required. I agree it would be better for it to be explicitly optional for single-hart platforms. Hopefully that can be incorporated in future specs. I've opened https://github.com/riscv/riscv-debug-spec/issues/389 to track this.

Tim

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