OpenSBI bring-up for custom platform

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Venkata Rao Gaddam

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Feb 14, 2022, 4:51:20 AM2/14/22
to RISC-V SW Dev
Greetings,

We are facing some issue in OpenSBI brining-up on new platform. 
Added config.mk, objects.mk and platform.c files to the customer platform folder then created a binary successfully by make PLATFORM=name and also tested with u-boot payload, but it is not booting on custom board. Properly added custom platform info into platform.c file but no luck. Also tried with DTS file by adding a binary into objects.mk, still no luck.

Please suggest that what to do to bring-up OpneSBI on my platform?


Best Regards,
Venkata Rao


merle w

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Feb 14, 2022, 5:02:02 AM2/14/22
to RISC-V SW Dev, venkatar...@gmail.com
The information you provided is a little short. What platform is unclear? opensbi has log output? Where are the logs stuck?

It is difficult to give you proper feedback without this information

Venkata Rao Gaddam

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Feb 14, 2022, 6:46:13 AM2/14/22
to RISC-V SW Dev, merl...@gmail.com, Venkata Rao Gaddam
Hi Merl,


Thanks for reply.

It is our new SoC platform with SCR7 64-bit RISC-V Processor and these details are entered in platform.c file and then created a opensbi binary. and that binary is  loaded into RAM through openOCD then resumed but no messages on console and it is blank. We tried this with dts file, but no messages over console. The BootROM is running successfully and messages coming over console also but not working after hand-off to opensbi binary, fw_payload.bin. The interrupts are also disable before jumping into openSBI.  

For details, please check attached opensbi platform files.


Best Regards,
Venkata Rao
platform.c
apss.dts
config.mk
objects.mk

Anup Patel

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Feb 14, 2022, 7:17:11 AM2/14/22
to Venkata Rao Gaddam, RISC-V SW Dev, merl...@gmail.com
Hi,

One issue I see is that you have apss.dtb linked to fw_payload.bin but
your platform.c does not have fw_platform_init() to inform location of
apss.dtb.

Try following changes:

1) Add these lines in your objects.mk
platform-padding-apss.o = 2048
platform-varprefix-apss.o = dt_apss

2) Add below code in your platform.c
extern const char dt_apss_start[];
unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
unsigned long arg2, unsigned long arg3, unsigned long arg4)
{
return (unsigned long)&dt_apss_start[0];
}

Regards,
Anup
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Venkata Rao Gaddam

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Feb 14, 2022, 7:40:27 AM2/14/22
to RISC-V SW Dev, Anup Patel, RISC-V SW Dev, merl...@gmail.com, Venkata Rao Gaddam
Hi Anup,

Thanks for reply.
We also tried without DTS, but no messages over console. And sure, will apply your suggestions and re-try.
I have another question, Do we need to do anything else in non-dts mode into the attached files.

Best Regards,
Venkata Rao

Anup Patel

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Feb 14, 2022, 8:05:39 AM2/14/22
to Venkata Rao Gaddam, RISC-V SW Dev, merl...@gmail.com
Hi Anup,

Just by looking at platform sources, I can't comment much.

You should try some debugger or print characters from assembly sources
by directly writing to the UART data register.

Regards,
Anup

On Mon, Feb 14, 2022 at 6:10 PM Venkata Rao Gaddam

Venkata Rao Gaddam

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Feb 14, 2022, 8:27:14 AM2/14/22
to RISC-V SW Dev, Anup Patel, RISC-V SW Dev, merl...@gmail.com, Venkata Rao Gaddam
Hi Anup,

Thank you for your inputs.
It is breaking before sbi_init() function and at ZERO bss and reset_regs() functions. 
This info is collected by openocd debugging.


Best Regards,
Venkata Rao 

merle w

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Feb 16, 2022, 11:08:46 AM2/16/22
to Venkata Rao Gaddam, RISC-V SW Dev, Anup Patel
Are the breaking at ZERO bss and reset_regs() functions random?
Is there some devices like a watchdog that needs to be disabled?

Venkata Rao Gaddam <venkatar...@gmail.com> 于2022年2月14日周一 21:27写道:

Venkata Rao Gaddam

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Feb 17, 2022, 4:41:43 AM2/17/22
to merle w, RISC-V SW Dev, Anup Patel
Hi Merie,


Thanks for your reply.
We have not implemented memory barriers in our design, hence issues are coming-up.
Now, we are entered into sbi_init() after disabling fence instructions in opensbi code.

 
Best Regards,
Venkata Rao



merle w

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Feb 17, 2022, 7:40:51 AM2/17/22
to Venkata Rao Gaddam, RISC-V SW Dev, Anup Patel
Great!

Venkata Rao Gaddam <venkatar...@gmail.com> 于2022年2月17日周四 17:41写道:
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